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L2 Auxiliary Control Register, EL1

The L2ACTLR_EL1 characteristics are:

Purpose

Provides configuration and control options for the L2 memory system.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RW RW RW RW RW

The L2ACTLR_EL1:

  • This register can be written only when the L2 memory system is idle. ARM recommends that you write to this register after a powerup reset before the MMU is enabled and before any ACE, CHI or ACP traffic has begun.

    If the register must be modified after a powerup reset sequence, to idle the L2 memory system, you must take the following steps:

    1. Disable the MMU from each core followed by an ISB to ensure the MMU disable operation is complete, then followed by a DSB to drain previous memory transactions.

    2. Ensure that the system has no outstanding AC channel coherence requests to the Cortex-A53 processor.

    3. Ensure that the system has no outstanding ACP requests to the Cortex-A53 processor.

When the L2 memory system is idle, the processor can update the L2ACTLR_EL1 followed by an ISB. After the L2ACTLR_EL1 is updated, the MMUs can be enabled and normal ACE and ACP traffic can resume.

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

L2ACTLR_EL1 is mapped to the AArch32 L2ACTLR register. See Auxiliary Control Register.

Attributes

L2ACTLR_EL1 is a 32-bit register.

Figure 4.60 shows the L2ACTLR_EL1 bit assignments.

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Table 4.109 shows the L2ACTLR_EL1 bit assignments.

Table 4.109. L2ACTLR_EL1 bit assignments
Bits Name Function
[31:30] -

L2 Victim Control.

0b10

This is the default value. Software must not change it.

[29] L2DEIEN

L2 cache data RAM error injection enable. The possible values are:

0

Normal behavior, errors are not injected. This is the reset value.

1

Double-bit errors are injected on all writes to the L2 cache data RAMs.

[28:25] -

Reserved, res0.

[24] L2TEIEN

L2 cache tag RAM error injection enable. The possible values are:

0

Normal behavior, errors are not injected. This is the reset value.

1

Double-bit errors are injected on all writes to the L2 cache tag RAMs.

[23:15] -

Reserved, res0.

[14] Enable UniqueClean evictions with data

Enables sending of WriteEvict transactions for UniqueClean evictions with data.

WriteEvict transactions update downstream caches that are outside the cluster. Enable WriteEvict transactions only if there is an L3 or system cache implemented in the system.

The possible values are:

0

Disables UniqueClean evictions with data. This is the reset value for ACE.

1

Enables UniqueClean evictions with data. This is the reset value for CHI.

Note

Some ACE interconnects might not support the WriteEvict transaction. You must not enable this bit if your interconnect does not support WriteEvict transactions.

[13:4] -

Reserved, res0.

[3] Disable clean/evict push to external

Disables sending of Evict transactions for clean cache lines that are evicted from the processor. This is required only if the external interconnect contains a snoop filter that requires notification when the processor evicts the cache line. The possible values are:

0

Enables clean/evict to be pushed out to external. This is the reset value for ACE.

1

Disables clean/evict from being pushed to external. This is the reset value for CHI.

[2:0] -

Reserved, res0.


To access the L2ACTLR_EL1:

	
MRS Rt, S3_1_C15_C0_0; Read L2ACTLR_EL1 into Rt
MSR S3_1_C15_C0_0, Rt; Write Rt to L2ACTLR_EL1
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