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Auxiliary Control Register, EL3

The ACTLR_EL3 characteristics are:

Purpose

Controls write access to implementation defined registers in EL2, such as CPUACTLR, CPUECTLR, L2CTLR, L2ECTLR and L2ACTLR.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW
Configurations

ACTLR_EL3 is mapped to AArch32 register ACTLR (S). See Auxiliary Control Register.

Attributes

ACTLR_EL3 is a 32-bit register.

Figure 4.30 shows the ACTLR_EL3 bit assignments.

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Table 4.74 shows the ACTLR_EL3 bit assignments.

Table 4.74. ACTLR_EL3 bit assignments
Bits Name Function
[31:7] -

Reserved, res0.

[6] L2ACTLR_EL1 access control

L2ACTLR_EL1 write access control. The possible values are:

0

The register is not write accessible from a lower exception level. This is the reset value.

1

The register is write accessible from EL2.

[5] L2ECTLR_EL1 access control

L2ECTLR_EL1 write access control. The possible values are:

0

The register is not write accessible from a lower exception level. This is the reset value.

1

The register is write accessible from EL2.

[4] L2CTLR_EL1 access control

L2CTLR_EL1 write access control. The possible values are:

0

The register is not write accessible from a lower exception level. This is the reset value.

1

The register is write accessible from EL2.

[3:2] - Reserved, res0.
[1] CPUECTLR_EL1 access control

CPUECTLR_EL1 write access control. The possible values are:

0

The register is not write accessible from a lower exception level. This is the reset value.

1

The register is write accessible from EL2.

[0] CPUACTLR_EL1 access control

CPUACTLR_EL1 write access control. The possible values are:

0

The register is not write accessible from a lower exception level. This is the reset value.

1

The register is write accessible from EL2.


To access the ACTLR_EL3:

	
MRS <Xt>, ACTLR_EL3 ; Read ACTLR_EL3 into Xt
MSR ACTLR_EL3, <Xt> ; Write Xt to ACTLR_EL3
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