The CLIDR_EL1 characteristics are:
The type of cache, or caches, implemented at each level.
The Level of Coherency and Level of Unification for the cache hierarchy.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
CLIDR_EL1 is architecturally mapped to AArch32 register CLIDR. See Cache Level ID Register.
CLIDR_EL1 is a 32-bit register.
Figure 4.22 shows the CLIDR_EL1 bit assignments.
Table 4.60 shows the CLIDR_EL1 bit assignments.
Indicates the Level of Unification Uniprocessor for the cache hierarchy:
Indicates the Level of Coherency for the cache hierarchy:
Indicates the Level of Unification Inner Shareable for the cache hierarchy:
Indicates the type of cache if the processor implements L3 cache:
Indicates the type of cache if the processor implements L2 cache:
Indicates the type of cache implemented at L1:
[a] If software reads the
Cache Type fields from Ctype1 upwards, after it has seen a value
To access the CLIDR_EL1:
MRS <Xt>, CLIDR_EL1 ; Read CLIDR_EL1 into Xt
Register access is encoded as follows: