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Cache Level ID Register

The CLIDR_EL1 characteristics are:

Purpose

Identifies:

  • The type of cache, or caches, implemented at each level.

  • The Level of Coherency and Level of Unification for the cache hierarchy.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RO RO RO RO RO
Configurations

CLIDR_EL1 is architecturally mapped to AArch32 register CLIDR. See Cache Level ID Register.

Attributes

CLIDR_EL1 is a 32-bit register.

Figure 4.22 shows the CLIDR_EL1 bit assignments.

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Table 4.60 shows the CLIDR_EL1 bit assignments.

Table 4.60. CLIDR_EL1 bit assignments
Bits Name Function
[31:30] -

Reserved, res0.

[29:27] LoUU

Indicates the Level of Unification Uniprocessor for the cache hierarchy:

0b001

L1 cache is the last level of cache that must be cleaned or invalidated when cleaning or invalidating to the point of unification for the processor.

[26:24] LoC

Indicates the Level of Coherency for the cache hierarchy:

0b001

L2 cache not implemented. A clean to the point of coherency operation requires the L1 cache to be cleaned.

0b010

L2 cache implemented. A clean to the point of coherency operation requires the L1 and L2 caches to be cleaned.

[23:21] LoUIS

Indicates the Level of Unification Inner Shareable for the cache hierarchy:

0b001

L2 cache.

L2 cache is the last level of cache that must be cleaned or invalidated when cleaning or invalidating to the point of unification for the Inner Shareable shareability domain.

[20:9] - Reserved, res0.
[8:6] Ctype3[a]

Indicates the type of cache if the processor implements L3 cache:

0b000

L3 cache not implemented.

[5:3] Ctype2

Indicates the type of cache if the processor implements L2 cache:

0b000

L2 cache not implemented.

0b100

Unified instruction and data caches at L2.

[2:0] Ctype1

Indicates the type of cache implemented at L1:

0b011

Separate instruction and data caches at L1.

[a] If software reads the Cache Type fields from Ctype1 upwards, after it has seen a value of 0b000, no caches exist at further-out levels of the hierarchy. So, for example, if Ctype2 is the first Cache Type field with a value of 0b000, the value of Ctype3 must be ignored.


To access the CLIDR_EL1:

	
MRS <Xt>, CLIDR_EL1 ; Read CLIDR_EL1 into Xt

Register access is encoded as follows:

Table 4.61. CLIDR_EL1 access encoding
op0 op1 CRn CRm op2
11 001 0000 0000 001

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