The CCSIDR_EL1 characteristics are:
Provides information about the architecture of the caches.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
CCSIDR_EL1 is architecturally mapped to AArch32 register CCSIDR. See Cache Size ID Register.
CCSIDR_EL1 is a 32-bit register.
Figure 4.21 shows the CCSIDR_EL1 bit assignments.
Table 4.58 shows the CCSIDR_EL1 bit assignments.
Indicates support for write-through:
Indicates support for write-back:
Indicates support for Read-Allocation:
Indicates support for Write-Allocation:
Indicates the number of sets in cache - 1. Therefore, a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2.
Indicates the associativity of cache - 1. Therefore, a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2.
Indicates the (log2 (number of words in cache line)) - 2:
Table 4.191 shows the individual bit field and complete register encodings for the CCSIDR_EL1. The CSSELR determines which CCSIDR_EL1 to select.
To access the CCSIDR_EL1:
MRS <Xt>, CCSIDR_EL1 ; Read CCSIDR_EL1 into Xt
Register access is encoded as follows: