You copied the Doc URL to your clipboard.

Cache Size Selection Register

The CSSELR_EL1 characteristics are:

Purpose

Selects the current Cache Size ID Register, by specifying:

  • The required cache level.

  • The cache type, either instruction or data cache.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RW RW RW RW RW
Configurations

CSSELR_EL1 is architecturally mapped to AArch32 register CSSELR(NS). See Cache Size Selection Register.

Attributes

CSSELR_EL1 is a 32-bit register.

Figure 4.23 shows the CSSELR_EL1 bit assignments.

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.62 shows the CSSELR_EL1 bit assignments.

Table 4.62. CSSELR_EL1 bit assignments
Bits Name Function
[31:4] -

Reserved, res0

[3:1] Level[a]

Cache level of required cache:

0b000

L1.

0b001

L2.

0b010-0b111

Reserved.

[0] InD[a]

Instruction not Data bit:

0

Data or unified cache.

1

Instruction cache.

[a] The combination of Level=0b001 and InD=1 is reserved.


To access the CSSELR_EL1:

	
MRS <Xt>, CSSELR_EL1 ; Read CSSELR_EL1 into Xt
MSR CSSELR_EL1, <Xt> ; Write Xt to CSSELR_EL1

Register access is encoded as follows:

Table 4.63. CSSELR_EL1 access encoding
op0 op1 CRn CRm op2
11 010 0000 0001 000

Was this page helpful? Yes No