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Cache Type Register

The CTR_EL0 characteristics are:

Purpose

Provides information about the architecture of the caches.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

Config RO RO RO RO RO

This register is accessible at EL0 when SCTLR_EL1.UCT is set to 1.

Configurations

CTR_EL0 is architecturally mapped to AArch32 register CTR. See Cache Type Register.

Attributes

CTR_EL0 is a 32-bit register.

Figure 4.24 shows the CTR_EL0 bit assignments.

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Table 4.64 shows the CTR_EL0 bit assignments.

Table 4.64. CTR_EL0 bit assignments
Bits Name Function
[31] -

Reserved, res1.

[30:28] -

Reserved, res0.

[27:24] CWG

Cache Write-Back granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified:

0x4

Cache Write-Back granule size is 16 words.

[23:20] ERG

Exclusives Reservation Granule. Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions:

0x4

Exclusive reservation granule size is 16 words.

[19:16] DminLine

Log2 of the number of words in the smallest cache line of all the data and unified caches that the processor controls:

0x4

Smallest data cache line size is 16 words.

[15:14] L1lp

L1 Instruction cache policy. Indicates the indexing and tagging policy for the L1 Instruction cache:

0b10

Virtually Indexed Physically Tagged (VIPT).

[13:4] -

Reserved, res0.

[3:0] IminLine

Log2 of the number of words in the smallest cache line of all the instruction caches that the processor controls.

0x4

Smallest instruction cache line size is 16 words.


To access the CTR_EL0:

	
MRS <Xt>, CTR_EL0 ; Read CTR_EL0 into Xt

Register access is encoded as follows:

Table 4.65. CTR_EL0 access encoding
op0 op1 CRn CRm op2
11 011 0000 0000 001

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