L2 Control Register
The L2CTLR_EL1 characteristics are:
- Purpose
-
Provides implementation defined control options for the L2 memory system.
- Usage constraints
-
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2 EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW Note
L2CTLR_EL1 is writeable. However, all writes to this register are ignored.
- Configurations
-
L2CTLR_EL1 is architecturally mapped to the AArch32 L2CTLR register. See Control Register.:
There is one L2CTLR_EL1 for the Cortex-A53 processor.
- Attributes
-
L2CTLR_EL1 is a 32-bit register.
Figure 4.58 shows the L2CTLR_EL1 bit assignments.
Table 4.107 shows the L2CTLR_EL1 bit assignments.
Bits | Name | Function |
---|---|---|
[31:26] | - |
Reserved, res0. |
[25:24] | Number of cores |
Number of cores present:
These bits are read-only and the value of this field is set to the number of cores present in the configuration. |
[23] | - |
Reserved, res0. |
[22] | CPU Cache Protection |
CPU Cache Protection. Core RAMs are implemented:
|
[21] | SCU-L2 Cache Protection |
SCU-L2 Cache Protection. L2 cache is implemented:
This field is RO. |
[20:6] | - |
Reserved, res0. |
[5] | L2 data RAM input latency |
L2 data RAM input latency:
This field is RO. |
[4:1] | - |
Reserved, res0. |
[0] | L2 data RAM output latency |
L2 data RAM output latency:
This field is RO. |
To access the L2CTLR_EL1:
MRS <Xt>, S3_1_C11_C0_2 ; Read L2CTLR_EL1 into Xt
MSR S3_1_C11_C0_2, <Xt>; Write Xt to L2CTLR_EL1