The CPUECTLR_EL1 characteristics are:
Provides additional implementation defined configuration and control options for the processor.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RW RW RW RW RW
The CPUECTLR_EL1 can be written dynamically.
The CPUECTLR_EL1 is write accessible in EL1 if ACTLR_EL3.CPUECTLR is 1 and ACTLR_EL2.CPUECTLR is 1, or ACTLR_EL3.CPUECTLR is 1 and SCR.NS is 0.
The CPUECTLR_EL1 is write accessible in EL2 if ACTLR_EL3.CPUECTLR is 1.
The CPUECTLR_EL1 is:
Architecturally mapped to the AArch32 CPUECTLR register. See CPU Extended Control Register.
CPUECTLR_EL1 is a 64-bit register.
Figure 4.72 shows the CPUECTLR_EL1 bit assignments.
Table 4.125 shows the CPUECTLR_EL1 bit assignments.
Enable hardware management of data coherency with other cores in the cluster. The possible values are:
Set the SMPEN bit before enabling the caches, even if there is only one core in the system.
Advanced SIMD and Floating-point retention control. The possible values are:
This field is present only if the Advanced SIMD and Floating-point Extension is implemented. Otherwise, it is res0.
CPU retention control. The possible values are:
To access the CPUECTLR_EL1:
MRS <Xt>, S3_1_C15_C2_1; Read EL1 CPU Extended Control Register MSR S3_1_C15_C2_1, <Xt>; Write EL1 CPU Extended Control Register