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Domain Access Control Register

The DACR32_EL2 characteristics are:

Purpose

Allows access to the AArch32 DACR register from AArch64 state only. Its value has no effect on execution in AArch64 state.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW RW RW
Configurations

DACR32_EL2 is architecturally mapped to AArch32 register DACR (NS). See Domain Access Control Register.

Attributes

DACR32_EL2 is a 32-bit register.

Figure 4.47 shows the DACR32_EL2 bit assignments.

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Table 4.91 shows the DACR32_EL2 bit assignments.

Table 4.91. DACR32_EL2 bit assignments
Bits Name Function
[31:0]

D<n>, bits [2n+1:2n], for n = 0 to 15

Domain n access permission, where n = 0 to 15. Permitted values are:

0b00

No access. Any access to the domain generates a Domain fault.

0b01

Client. Accesses are checked against the permission bits in the translation tables.

0b11

Manager. Accesses are not checked against the permission bits in the translation tables.

The value 0b10 is reserved.


To access the DACR32_EL2:

	
MRS <Xt>, DACR32_EL2 ; Read DACR32_EL2 into Xt
MSR DACR32_EL2, <Xt> ; Write Xt to DACR32_EL2
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