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Exception Syndrome Register, EL2

The ESR_EL2 characteristics are:

Purpose

Holds syndrome information for an exception taken to EL2.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW RW RW
Configurations

ESR_EL2 is architecturally mapped to AArch32 register HSR. See Hyp Syndrome Register.

Attributes

ESR_EL2 is a 32-bit register.

Figure 4.53 shows the ESR_EL2 bit assignments.

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Table 4.100 shows the ESR_EL2 bit assignments.

Table 4.100.  ESR_EL2 bit assignments
Bits Name Function
[31:26] EC Exception Class. Indicates the reason for the exception that this register holds information about.
[25] IL

Instruction Length for synchronous exceptions. The possible values are:

0

16-bit.

1

32-bit.

[24:0] ISS

Syndrome information.


When the EC field is 0x2F, indicating an SError interrupt has occurred, the ISS field contents are IMPLEMENTATION DEFINED. Table 4.101 shows the definition of the ISS field contents for the Cortex-A53 processor.

Table 4.101. ISS field contents for the Cortex-A53 processor
ISS[23:22] ISS[1:0] Description
0b00 0b00

DECERR on external access

0b00 0b01

Double-bit error detected on dirty line in L2 cache

0b00 0b10

SLVERR on external access

0b01 0b00

nSEI , or nVSEI in a guest OS, asserted

0b01 0b01

nREI asserted


To access the ESR_EL2:

	
MRS <Xt>, ESR_EL2 ; Read EL1 Exception Syndrome Register
MSR ESR_EL2, <Xt> ; Write EL1 Exception Syndrome Register
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