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Fault Address Register, EL1

The FAR_EL1 characteristics are:

Purpose

Holds the faulting Virtual Address for all synchronous instruction or data aborts, or exceptions from a misaligned PC or a Watchpoint debug event, taken to EL1.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RW RW RW RW RW
Configurations

FAR_EL1[31:0] is architecturally mapped to AArch32 register DFAR (NS). See Data Fault Address Register.

FAR_EL1[63:32] is architecturally mapped to AArch32 register IFAR (NS). See Instruction Fault Address Register.

Attributes

FAR_EL1 is a 64-bit register.

Figure 4.55 shows the FAR_EL1 bit assignments.

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Table 4.104Table 4.104 shows the FAR_EL1 bit assignments.

Table 4.104.  FAR_EL1 bit assignments
Bits Name Function
[63:0] VA

The faulting Virtual Address for all synchronous instruction or data aborts, or an exception from a misaligned PC, taken in EL1.

If a memory fault that sets the FAR is generated from one of the data cache instructions, this field holds the address specified in the register argument of the instruction.


To access the FAR_EL1:

	
MRS <Xt>, FAR_EL1 ; Read EL1 Fault Address Register
MSR FAR_EL1, <Xt> ; Write EL1 Fault Address Register
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