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Fault Address Register, EL2

The FAR_EL2 characteristics are:

Purpose

Holds the faulting Virtual Address for all synchronous instruction or data aborts, or exceptions from a misaligned PC or a Watchpoint debug event, taken to EL2.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW RW RW
Configurations

FAR_EL2[31:0] is architecturally mapped to AArch32 registers:

FAR_EL2[63:32] is architecturally mapped to AArch32 registers:

Attributes

FAR_EL2 is a 64-bit register.

Figure 4.56 shows the FAR_EL2 bit assignments.

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Table 4.105 Table 4.104 shows the FAR_EL2 bit assignments.

Table 4.105.  FAR_EL2 bit assignments
Bits Name Function
[63:0] VA

The faulting Virtual Address for all synchronous instruction or data aborts, or an exception from a misaligned PC, taken in EL2.

If a memory fault that sets the FAR is generated from one of the data cache instructions, this field holds the address specified in the register argument of the instruction.


To access the FAR_EL2:

	
MRS <Xt>, FAR_EL2 ; Read EL2 Fault Address Register
MSR FAR_EL2, <Xt> ; Write EL2 Fault Address Register
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