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Hyp Debug Control Register

The MDCR_EL2 characteristics are:

Purpose

Controls the trapping to Hyp mode of Non-secure accesses, at EL1 or lower, to functions provided by the debug and trace architectures and the Performance Monitor.

Usage constraints

This register is accessible as follows:

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW RW RW
Configurations
  • MDCR_EL2 is architecturally mapped to AArch32 register HDCR. See Hyp Debug Control Register .

  • This register is accessible only at EL2 or EL3.

Attributes

MDCR_EL2 is a 32-bit register.

Figure 4.34 shows the MDCR_EL2 bit assignments.

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Table 4.78 shows the MDCR_EL2 bit assignments.

Table 4.78. MDCR_EL2 bit assignments
Bits Name Function
[31:12] -

Reserved, res0.

[11] TDRA

Trap debug ROM address register access.

0

Has no effect on accesses to debug ROM address registers from EL1 and EL0.

1

Trap valid Non-secure EL1 and EL0 access to debug ROM address registers to Hyp mode.

When this bit is set to 1, any access to the following registers from EL1 or EL0 is trapped to EL2:

  • AArch32: DBGDRAR, DBGDSAR.

  • AArch64: MDRAR_EL1.

If HCR_EL2.TGE is 1 or MDCR_EL2.TDE is 1, then this bit is ignored and treated as though it is 1 other than for the value read back from MDCR_EL2.

On Warm reset, the field resets to 0.

[10] TDOSA

Trap Debug OS-related register access:

0

Has no effect on accesses to OS-related debug registers.

1

Trap valid Non-secure accesses to OS-related debug registers to EL2.

When this bit is set to 1, any access to the following registers from EL1 or EL0 is trapped to EL2:

  • AArch32: DBGOSLAR, DBGOSLSR, DBGOSDLR, DBGPRCR.

  • AArch64: OSLAR_EL1, OSLSR_EL1, OSDLR_EL1, DBGPRCR_EL1.

If HCR_EL2.TGE is 1 or MDCR_EL2.TDE is 1, then this bit is ignored and treated as though it is 1 other than for the value read back from MDCR_EL2.

On Warm reset, the field resets to 0.

[9] TDA

Trap Debug Access:

0

Has no effect on accesses to Debug registers.

1

Trap valid Non-secure accesses to Debug registers to EL2.

When this bit is set to 1, any valid Non-secure access to the debug registers from EL1 or EL0, other than the registers trapped by the TDRA and TDOSA bits, is trapped to EL2.

If HCR_EL2.TGE is 1 or MDCR_EL2.TDE is1, then this bit is ignored and treated as though it is 1 other than for the value read back from MDCR_EL2.

On Warm reset, the field resets to 0.

[8] TDE

Trap software debug exceptions:

0

Has no effect on software debug exceptions.

1

Route Software debug exceptions from Non-secure EL1 and EL0 to EL2. Also enables traps on all debug register accesses to EL2.

If HCR_EL2.TGE is 1, then this bit is ignored and treated as though it is 1 other than for the value read back from MDCR_EL2.This bit resets to 0.

[7] HPME

Hypervisor Performance Monitor Enable:

0

EL2 performance monitor counters disabled.

1

EL2 performance monitor counters enabled.

When this bit is set to 1, the Performance Monitors counters that are reserved for use from EL2 or Secure state are enabled. For more information see the description of the HPMN field.

The reset value of this bit is unknown.

[6] TPM

Trap Performance Monitor accesses:

0

Has no effect on performance monitor accesses.

1

Trap Non-secure EL0 and EL1 accesses to Performance Monitors registers that are not unallocated to EL2.

This bit resets to 0.

[5] TPMCR

Trap PMCR_EL0 accesses:

0

Has no effect on PMCR_EL0 accesses.

1

Trap Non-secure EL0 and EL1 accesses to PMCR_EL0 to EL2.

This bit resets to 0.

See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

[4:0] HPMN

Hyp Performance Monitor count. Defines the number of Performance Monitors counters that are accessible from Non-secure EL1 and EL0 modes.

In Non-secure state, HPMN divides the Performance Monitors counters as follows. For counter n in Non-secure state:

For example, If PMnEVCNTR is performance monitor counter n then, in Non-secure state:

  • If n is in the range 0 ≤ n < HPMN, the counter is accessible from EL1 and EL2, and from EL0 if permitted by PMUSERENR_EL0. PMCR_EL0.E enables the operation of counters in this range.

  • If n is in the range HPMN ≤ n < 6[a], the counter is accessible only from EL2. MDCR_EL2.HPME enables the operation of counters in this range.

If the field is set to 0, then Non-secure EL0 or EL1 has no access to any counters.

If the field is set to a value greater than six, the behavior is the same as if the value is six.

For reads of MDCR_EL2.HPMN by EL2 or higher, if this field is set to 0 or to a value larger than PMCR_EL0.N, the processor returns the value that was written to MDCR_EL2.HPMN.

This field resets to 0x6.

[a] There are six performance counters, specified by PMCR.N.


To access the MDCR_EL2:

	
MRS <Xt>, MDCR_EL2 ; Read MDCR_EL2 into Xt
MSR MDCR_EL2, <Xt> ; Write Xt to MDCR_EL2
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