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Hyp System Trap Register

The HSTR_EL2 characteristics are:

Purpose

Controls access to ThumbEE and coprocessor registers at lower exception levels in AArch32.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW RW RW
Configurations

HSTR_EL2 is architecturally mapped to AArch32 register HSTR. See Hyp System Trap Register.

Attributes

HSTR_EL2 is a 32-bit register.

Figure 4.36 shows the HSTR_EL2 bit assignments.

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Table 4.80 shows the HSTR_EL2 bit assignments.

Table 4.80. HSTR_EL2 bit assignments
Bits Name Function
[31:17] -

Reserved, res0.

[16] TTEE

Trap T32EE. This value is:

0

T32EE is not supported.

[15] T15

Trap coprocessor primary register CRn = 15. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 15 to Hyp mode.

The reset value is 0.

[14] -

Reserved, res0.

[13] T13

Trap coprocessor primary register CRn = 13. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 13 to Hyp mode.

The reset value is 0.

[12] T12

Trap coprocessor primary register CRn = 12. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 12 to Hyp mode.

The reset value is 0.

[11] T11

Trap coprocessor primary register CRn = 11. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 11 to Hyp mode.

The reset value is 0.

[10] T10

Trap coprocessor primary register CRn = 10. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 10 to Hyp mode.

The reset value is 0.

[9] T9

Trap coprocessor primary register CRn = 9. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 9 to Hyp mode.

The reset value is 0.

[8] T8

Trap coprocessor primary register CRn = 8. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 8 to Hyp mode.

The reset value is 0.

[7] T7

Trap coprocessor primary register CRn = 7. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 7 to Hyp mode.

The reset value is 0.

[6] T6

Trap coprocessor primary register CRn = 6. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 6 to Hyp mode.

The reset value is 0.

[5] T5

Trap coprocessor primary register CRn = 5. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 5 to Hyp mode.

The reset value is 0.

[4] - Reserved, res0.
[3] T3

Trap coprocessor primary register CRn = 3. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 3 to Hyp mode.

The reset value is 0.

[2] T2

Trap coprocessor primary register CRn = 2. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 2 to Hyp mode.

The reset value is 0.

[1] T1

Trap coprocessor primary register CRn = 1. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 1 to Hyp mode.

The reset value is 0.

[0] T0

Trap coprocessor primary register CRn = 0. The possible values are:

0

Has no effect on Non-secure accesses to CP15 registers.

1

Trap valid Non-secure accesses to coprocessor primary register CRn = 0 to Hyp mode.

The reset value is 0.


To access the HSTR_EL2:

	
MRS <Xt>, HSTR_EL2 ; Read HSTR_EL2 into Xt
MSR HSTR_EL2, <Xt> ; Write Xt to HSTR_EL2
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