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Hypervisor Configuration Register

The HCR_EL2 characteristics are:

Purpose

Provides configuration control for virtualization, including whether various Non-secure operations are trapped to EL2.

HCR_EL2 is part of the Hypervisor and virtualization registers functional group.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW RW RW
Configurations

HCR_EL2[31:0] is architecturally mapped to AArch32 register HCR. See Hyp Configuration Register .

HCR_EL2[63:32] is architecturally mapped to AArch32 register HCR2. See Hyp Configuration Register 2.

Attributes

HCR_EL2 is a 64-bit register.

Figure 4.33 shows the HCR_EL2 bit assignments.

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Table 4.77 shows the HCR_EL2 bit assignments.

Table 4.77.  HCR_EL2 bit assignments
Bits Name Function
[63:34] -

Reserved, res0.

[33] ID

Disables stage 2 instruction cache. When HCR_EL2.VM is 1, this forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable for the EL1/EL0 translation regimes. The possible values are:

0

Has no effect on stage 2 EL1/EL0 translation regime for instruction accesses. This is the reset value.

1

Forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable for the EL1/EL0 translation regime.

[32] CD

Disables stage 2 data cache. When HCR_EL2.VM is 1, this forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the EL1/EL0 translation regimes. The possible values are:

0

Has no effect on stage 2 EL1/EL0 translation regime for data access or translation table walks. This is the reset value.

1

Forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the EL1/EL0 translation regime.

[31] RW

Register width control for lower exception levels. The possible values are:

0

Lower levels are all AArch32. This is the reset value.

1

EL1 is AArch64. EL0 is determined by the register width described in the current processing state when executing at EL0.

[30] TRVM

Trap reads of Virtual Memory controls.[a] The possible values are:

0

Non-secure EL1 reads are not trapped. This is the reset value.

1

Non-secure EL1 reads are trapped to EL2.

[29] HCD Reserved, res0.
[28] TDZ

Traps DC ZVA instruction. The possible values are:

0

DC ZVA instruction is not trapped. This is the reset value.

1

DC ZVA instruction is trapped to EL2 when executed in Non-secure EL1 or EL0.

[27] TGE

Traps general exceptions. If this bit is set, and SCR_EL3.NS is set, then:

  • All Non-secure EL1 exceptions are routed to EL2.

  • For Non-secure EL1, the SCTLR_EL1.M bit is treated as 0 regardless of its actual state other than the purpose of reading the bit.

  • The HCR_EL2.FMO, HCR_EL2.IMO, and HCR_EL2.AMO bits are treated as 1 regardless of their actual state other than for the purpose of reading the bits.

  • All virtual interrupts are disabled.

  • Any implementation defined mechanisms for signaling virtual interrupts are disabled.

  • An exception return to Non-secure EL1 is treated as an illegal exception return.

[26] TVM

Trap virtual memory controls.[a] The possible values are:

0

Non-secure EL1 writes are not trapped. This is the reset value.

1

Non-secure EL1 writes are trapped to EL2.

[25] TTLB

Traps TLB maintenance instructions.[a] The possible values are:

0

Non-secure EL1 TLB maintenance instructions are not trapped. This is the reset value.

1

TLB maintenance instructions executed from Non-secure EL1that are not undefined are trapped to EL2.

[24] TPU

Traps cache maintenance instructions to Point of Unification (POU).[a] The possible values are:

0

Cache maintenance instructions are not trapped. This is the reset value.

1

Cache maintenance instructions to the POU executed from Non-secure EL1 or EL0 that are not undefined are trapped to EL2.

[23] TPC

Traps data or unified cache maintenance instructions to Point of Coherency (POC).[a] The possible values are:

0

Data or unified cache maintenance instructions are not trapped. This is the reset value.

1

Data or unified cache maintenance instructions by address to the POC executed from Non-secure EL1 or EL0 that are not undefined are trapped to EL2.

[22] TSW

Traps data or unified cache maintenance instructions by Set or Way.[a] The possible values are:

0

Data or unified cache maintenance instructions are not trapped. This is the reset value.

1

Data or unified cache maintenance instructions by Set or Way executed from Non-secure EL1 that are not undefined are trapped to EL2.are not trapped.

[21] TACR

Traps Auxiliary Control registers. The possible values are:

0

Accesses to Auxiliary Control registers are not trapped. This is the reset value.

1

Accesses to ACTLR in AArch32 state or the ACTLR_EL1 in the AArch64 state from Non-secure EL1 are trapped to EL2.

[20] TIDCP

Trap Implementation Dependent functionality. When 1, this causes accesses to the following instruction set space executed from Non-secure EL1 to be trapped to EL2:

AArch32

All CP15 MCR and MRC instructions as follows:

  • CRn is 9, Opcode1 is 0 to 7, CRm is c0, c1, c2, c5, c6, c7, or c8, and Opcode2 is 0 to 7.

  • CRn is 10, Opcode1 is 0 to 7, CRm is c0, c1, c4, or c8, and Opcode2 is 0 to 7.

  • CRn is 11, Opcode1 is 0 to 7, CRm is c0 to c8, or c15, and Opcode2 is 0 to 7.

AArch64

Reserved control space for implementation defined functionality.

Accesses from EL0 are undefined. The reset value is 0.

[19] TSC

Traps SMC instruction. The possible values are:

0

SMC instruction in not trapped. This is the reset value.

1

SMC instruction executed in Non-secure EL1 is trapped to EL2 for AArch32 and AArch64 Execution states.

[18] TID3

Traps ID group 3 registers.[a] The possible values are:

0

ID group 3 register accesses are not trapped. This is the reset value.

1

Reads to ID group 3 registers executed from Non-secure EL1 are trapped to EL2.

[17] TID2

Traps ID group 2 registers.[a] The possible values are:

0

ID group 2 register accesses are not trapped. This is the reset value.

1

Reads to ID group 2 registers and writes to CSSELR and CSSELR_EL1executed from Non-secure EL1 or EL0, if not undefined, are trapped to EL2.

[16] TID1

Traps ID group 1 registers.[a] The possible values are:

0

ID group 1 register accesses are not trapped. This is the reset value.

1

Reads to ID group 1registers executed from Non-secure EL1 are trapped to EL2.

[15] TID0

Traps ID group 0 registers.[a] The possible values are:

0

ID group 0 register accesses are not trapped. This is the reset value.

1

Reads to ID group 0 registers executed from Non-secure EL1 are trapped to EL2.

[14] TWE

Traps WFE instruction if it would cause suspension of execution. For example, if there is no pending WFE event. The possible values are:

0

WFE instruction is not trapped. This is the reset value.

1

WFE instruction executed in Non-secure EL1 or EL0 is trapped to EL2 for AArch32 and AArch64 Execution states.

[13] TWI

Traps WFI instruction if it causes suspension of execution. For example, if there is no pending WFI event. The possible values are:

0

WFI instruction is not trapped. This is the reset value.

1

WFI instruction executed in Non-secure EL1 or EL0 is trapped to EL2 for AArch32 and AArch64 Execution states.

[12] DC

Default cacheable. When this bit is set it causes:

  • SCTLR_EL1.M to behave as 0 for all purposes other than reading the bit.

  • HCR_EL2.VM to behave as 1 for all purposes other than reading the bit.

The memory type produced by the first stage of translation in Non-secure EL1 and EL0 is Non-Shareable, Inner Write-Back Write-Allocate, Outer Write-Back Write-Allocate. The reset value is 0.

[11:10] BSU

Barrier shareability upgrade. Determines the minimum shareability domain that is supplied to any barrier executed from Non-secure EL1 or EL0. The possible values are:

0b00

No effect. This is the reset value.

0b01

Inner Shareable.

0b10

Outer Shareable.

0b11

Full system.

This value is combined with the specified level of the barrier held in its instruction, according to the algorithm for combining shareability attributes.

[9] FB

Forces broadcast.[b] The possible values are:

0

Instructions are not broadcast. This is the reset value.

1

Forces instruction broadcast within Inner Shareable domain when executing from Non-secure EL1.

[8] VSE

Virtual System Error/Asynchronous Abort. The possible values are:

0

Virtual System Error/Asynchronous Abort is not pending by this mechanism. This is the reset value.

1

Virtual System Error/Asynchronous Abort is pending by this mechanism.

The virtual System Error/Asynchronous Abort is enabled only when the HCR_EL2.AMO bit is set.

[7] VI

Virtual IRQ interrupt. The possible values are:

0

Virtual IRQ is not pending by this mechanism. This is the reset value.

1

Virtual IRQ is pending by this mechanism.

The virtual IRQ is enabled only when the HCR_EL2.IMO bit is set.

[6] VF

Virtual FIQ interrupt. The possible values are:

0

Virtual FIQ is not pending by this mechanism. This is the reset value.

1

Virtual FIQ is pending by this mechanism.

The virtual FIQ is enabled only when the HCR_EL2.FMO bit is set.

[5] AMO

Asynchronous abort and error interrupt routing. The possible values are:

0

Asynchronous external Aborts and SError Interrupts while executing at exception levels lower than EL2 are not taken at EL2. Virtual System Error/Asynchronous Abort is disabled. This is the reset value.

1

Asynchronous external Aborts and SError Interrupts while executing at EL2 or lower are taken in EL2 unless routed by SCTLR_EL3.EA bit to EL3. Virtual System Error/Asynchronous Abort is enabled.

[4] IMO

Physical IRQ routing. The possible values are:

0

Physical IRQ while executing at exception levels lower than EL2 are not taken at EL2. Virtual IRQ interrupt is disabled. This is the reset value.

1

Physical IRQ while executing at EL2 or lower are taken in EL2 unless routed by SCTLR_EL3.IRQ bit to EL3. Virtual IRQ interrupt is enabled.

[3] FMO

Physical FIQ routing. The possible values are:

0

Physical FIQ while executing at exception levels lower than EL2 are not taken at EL2. Virtual FIQ interrupt is disabled. This is the reset value.

1

Physical FIQ while executing at EL2 or lower are taken in EL2 unless routed by SCTLR_EL3.FIQ bit to EL3. Virtual FIQ interrupt is enabled.

[2] PTW

Protected Table Walk. When this bit is set, if the stage 2 translation of a translation table access, made as part of a stage 1 translation table walk at EL0 or EL1, maps to Device memory, the access is faulted as a stage 2 Permission fault. The reset value is 0.

[1] SWIO

Set/Way Invalidation Override. Non-secure EL1 execution of the data cache invalidate by set/way instruction is treated as data cache clean and invalidate by set/way. When this bit is set:

  • DCISW is treated as DCCISW when in the AArch32 Execution state.

  • DC ISW is treated as DC CISW when in the AArch64 Execution state.

This bit is res1.

[0] VM

Enables second stage of translation. The possible values are:

0

Disables second stage translation. This is the reset value.

1

Enables second stage translation for execution in Non-secure EL1 and EL0.

[a] See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for the registers covered by this setting.

[b] See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for the instructions covered by this setting.


To access the HCR_EL2:

	
MRS <Xt>, HCR_EL2 ; Read HCR_EL2 into Xt
MSR HCR_EL2, <Xt> ; Write Xt to HCR_EL2
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