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Instruction Fault Status Register, EL2

The IFSR32_EL2 characteristics are:

Purpose

Allows access to the AArch32 IFSR register from AArch64 state only. Its value has no effect on execution in AArch64 state.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW RW RW
Configurations

IFSR32_EL2 is architecturally mapped to AArch32 register IFSR(NS). See Instruction Fault Status Register.

Attributes

IFSR32_EL2 is a 32-bit register.

There are two formats for this register. The current translation table format determines which format of the register is used. This section describes:

IFSR32_EL2 when using the Short-descriptor translation table format

Figure 4.51 shows the IFSR32_EL2 bit assignments when using the Short-descriptor translation table format.

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Table 4.96 shows the IFSR32_EL2 bit assignments when using the Short-descriptor translation table format.

Table 4.96. IFSR32_EL2 bit assignments for Short-descriptor translation table format
Bits Name Function
[31:13] -

Reserved, res0.

[12] ExT

External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:

0

External abort marked as DECERR.

1

External abort marked as SLVERR.

For aborts other than external aborts this bit always returns 0.

[11] -

Reserved, res0.

[10] FS[4] Part of the Fault Status field. See bits [3:0] in this table.
[9] -

RAZ.

[8:5] -

Reserved, res0.

[4:0] FS[3:0]

Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved.

0b00010

Debug event.

0b00011

Access flag fault, section.

0b00101

Translation fault, section.

0b00110

Access flag fault, page.

0b00111

Translation fault, page.

0b01000

Synchronous external abort, non-translation.

0b01001

Domain fault, section.

0b01011

Domain fault, page.

0b01100

Synchronous external abort on translation table walk, first level.

0b01101

Permission Fault, Section.

0b01110

Synchronous external abort on translation table walk, second Level.

0b01111

Permission fault, page.

0b10000

TLB conflict abort.

0b11001

Synchronous parity error on memory access.

0b11100

Synchronous parity error on translation table walk, first level.

0b11110

Synchronous parity error on translation table walk, second level.


IFSR32_EL2 when using the Long-descriptor translation table format

Figure 4.52 shows the IFSR32_EL2 bit assignments when using the Long-descriptor translation table format.

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Table 4.97 shows the IFSR32_EL2 bit assignments when using the Long-descriptor translation table format.

Table 4.97. IFSR32_EL2 bit assignments for Long-descriptor translation table format
Bits Name Function
[31:13] -

Reserved, res0.

[12] ExT

External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:

0

External abort marked as DECERR.

1

External abort marked as SLVERR.

For aborts other than external aborts this bit always returns 0.

[11:10] -

Reserved, res0.

[9] -

RAO.

[8:6] -

Reserved, res0.

[5:0] Status

Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved.

0b000000

Address size fault in TTBR0 or TTBR1.

0b0001LL

Translation fault, LL bits indicate level.

0b0010LL

Access fault flag, LL bits indicate level.

0b0011LL

Permission fault, LL bits indicate level.

0b010000

Synchronous external abort.

0b0101LL

Synchronous external abort on translation table walk, LL bits indicate level.

0b011000

Synchronous parity error on memory access.

0b0111LL

Synchronous parity error on memory access on translation table walk, LL bits indicate level.

0b100001

Alignment fault.

0b100010

Debug event.

0b110000

TLB conflict abort.


Table 4.98 shows how the LL bits in the Status field encode the lookup level associated with the MMU fault.

Table 4.98. Encodings of LL bits associated with the MMU fault
Bits Meaning
0b00 Reserved
0b01 Level 1
0b10 Level 2
0b11 Level 3

Note

If a Data Abort exception is generated by an instruction cache maintenance operation when the Long-descriptor translation table format is selected, the fault is reported as a Cache Maintenance fault in the DFSR or HSR with the appropriate Fault Status code. For such exceptions reported in the DFSR, the corresponding IFSR32_EL2 is unknown.

To access the IFSR32_EL2:

	
MRS <Xt>, IFSR32_EL2 ; Read IFSR32_EL2 into Xt
MSR IFSR32_EL2, <Xt> ; Write Xt to IFSR32_EL2

Register access is encoded as follows:

Table 4.99. IFSR32_EL2 access encoding
op0 op1 CRn CRm op2
11 000 0101 0000 001

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