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Memory Attribute Indirection Register, EL1

The MAIR_EL1 characteristics are:

Purpose

Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL1.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RW RW RW RW RW

MAIR_EL1 is permitted to be cached in a TLB.

Configurations

MAIR_EL1[31:0] is architecturally mapped to AArch32 register:

MAIR_EL1[63:32] is architecturally mapped to AArch32 register:

Attributes

MAIR_EL1 is a 64-bit register.

Figure 4.64 shows the MAIR_EL1 bit assignments.

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Attr<n> is the memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where AttrIndx[2:0] gives the value of <n> in Attr<n>.

Table 4.113 shows the encoding of bits [7:4] of the Attr<n> field.

Table 4.113. Attr<n>[7:4] bit assignments
Bits Meaning
0b0000 Device memory. See Table 4.114 for the type of Device memory.
0b00RW, RW not 00 Normal Memory, Outer Write-through transient.[a]
0b0100 Normal Memory, Outer Non-Cacheable.
0b01RW, RW not 00 Normal Memory, Outer Write-back transient.[a]
0b10RW Normal Memory, Outer Write-through non-transient.
0b11RW Normal Memory, Outer Write-back non-transient.

[a] The transient hint is ignored.


Table 4.114 shows the encoding of bits [0:3] of the Attr<n> field.

Table 4.114. Attr<n>[3:0] bit assignments
Bits Meaning when Attr<n>[7:4] is 0000 Meaning when Attr<n>[7:4] is not 0000
0b0000 Device-nGnRnE memory unpredictable
0b00RW, RW not 00 unpredictable Normal Memory, Inner Write-through transient
0b0100 Device-nGnRE memory Normal memory, Inner Non-Cacheable
0b01RW, RW not 00 unpredictable Normal Memory, Inner Write-back transient
0b1000 Device-nGRE memory Normal Memory, Inner Write-throughnon-transient (RW=00)
0b10RW, RW not 00 unpredictable Normal Memory, Inner Write-through non-transient
0b1100 Device-GRE memory Normal Memory, Inner Write-back non-transient (RW=00)
0b11RW, RW not 00 unpredictable Normal Memory, Inner Write-back non-transient

Table 4.115 shows the encoding of the R and W bits that are used, in some Attr<n> encodings in Table 4.113 and Table 4.114, to define the read-allocate and write-allocate policies:

Table 4.115. Encoding of R and W bits in some Attrm fields
R or W Meaning
0 Do not allocate
1 Allocate

To access the MAIR_EL1:

	
MRS <Xt>, MAIR_EL1 ; Read EL1 Memory Attribute Indirection Register
MSR MAIR_EL1, <Xt> ; Write EL1 Memory Attribute Indirection Register
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