The MAIR_EL3 characteristics are:
Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL3.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - - RW RW
MAIR_EL2 is permitted to be cached in a TLB.
MAIR_EL3[31:0] is mapped to AArch32 register PRRR (S) when TTBCR.EAE is 0. See Primary Region Remap Register.
MAIR_EL3[63:32] is mapped to AArch32 register NMRR (S) when TTBCR.EAE is 0. See Normal Memory Remap Register.
MAIR_EL3 is a 64-bit register.
The MAIR_EL3 bit assignments follow the same pattern as described in Figure 4.64.
To access the MAIR_EL3:
MRS <Xt>, MAIR_EL3 ; Read EL3 Memory Attribute Indirection Register MSR MAIR_EL3, <Xt> ; Write EL3 Memory Attribute Indirection Register