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Memory Attribute Indirection Register, EL3

The MAIR_EL3 characteristics are:

Purpose

Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL3.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW

MAIR_EL2 is permitted to be cached in a TLB.

Configurations

MAIR_EL3[31:0] is mapped to AArch32 register PRRR (S) when TTBCR.EAE is 0. See Primary Region Remap Register.

MAIR_EL3[63:32] is mapped to AArch32 register NMRR (S) when TTBCR.EAE is 0. See Normal Memory Remap Register.

Attributes

MAIR_EL3 is a 64-bit register.

The MAIR_EL3 bit assignments follow the same pattern as described in Figure 4.64.

The description of the MAIR_EL3 bit assignments are the same as described in Table 4.113 and Table 4.116.

To access the MAIR_EL3:

	
MRS <Xt>, MAIR_EL3 ; Read EL3 Memory Attribute Indirection Register
MSR MAIR_EL3, <Xt> ; Write EL3 Memory Attribute Indirection Register
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