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Monitor Debug Configuration Register, EL3

The MDCR_EL3 characteristics are:

Purpose

Provides configuration options for Security to self-hosted debug.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW
Configurations

MDCR_EL3 is mapped to AArch32 register SDCR. See Secure Debug Control Register.

Attributes

MDCR_EL3 is a 32-bit register.

Figure 4.43 shows the MDCR_EL3 bit assignments.

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Table 4.87 shows the MDCR_EL3 bit assignments.

Table 4.87.  MDCR_EL3 bit assignments
Bits Name Function
[31:22] -

Reserved, res0.

[21] EPMAD

External debugger access to Performance Monitors registers disabled. This disables access to these registers by an external debugger. The possible values are:

0

Access to Performance Monitors registers from external debugger is permitted.

1

Access to Performance Monitors registers from external debugger is disabled, unless overridden by authentication interface.

[20] EDAD

External debugger access to breakpoint and watchpoint registers disabled. This disables access to these registers by an external debugger. The possible values are:

0

Access to breakpoint and watchpoint registers from external debugger is permitted.

1

Access to breakpoint and watchpoint registers from external debugger is disabled, unless overridden by authentication interface.

[19:18] -

Reserved, res0.

[17] SPME

Secure performance monitors enable. This enables event counting exceptions from Secure state. The possible values are:

0

Event counting prohibited in Secure state. This is the reset value.

1

Event counting allowed in Secure state.

[16] SDD

AArch64 secure debug disable. Disables Software debug exceptions from Secure state if Secure EL1 is using AArch64, other than from Software breakpoint instructions. The possible values are:

0

Debug exceptions from Secure EL0 are enabled, and debug exceptions from Secure EL1 are enabled if MDSCR_EL1.KDE is 1 and PSTATE.D is 0.

1

Debug exceptions from all exception levels in Secure state are disabled.

The reset value is unknown.

[15:14] SPD32

AArch32 secure privileged debug. Enables or disables debug exceptions from Secure state if Secure EL1 is using AArch32, other than Software breakpoint instructions. The possible values are:

0b00

Legacy mode. Debug exceptions from Secure EL1 are enabled only if AArch32SelfHostedSecurePrivilegedInvasiveDebugEnabled().

0b01

Reserved.

0b10

Secure privileged debug disabled. Debug exceptions from Secure EL1 are disabled.

0b11

Secure privileged debug enabled. Debug exceptions from Secure EL1 are enabled.

The reset value is unknown.

[13:11] -

Reserved, res0.

[10] TDOSA

Trap accesses to the OS debug system registers, OSLAR_EL1, OSLSR_EL1, OSDLR_EL1, and DBGPRCR_EL1 OS.

0

Accesses are not trapped.

1

Accesses to the OS debug system registers are trapped to EL3.

The reset value is unknown.

[9] TDA

Trap accesses to the remaining sets of debug registers to EL3.

0

Accesses are not trapped.

1

Accesses to the remaining debug system registers are trapped to EL3.

The reset value is unknown.

[8:7] -

Reserved, res0.

[6] TPM

Trap Performance Monitors accesses. The possible values are:

0

Accesses are not trapped.

1

Accesses to the Performance Monitor registers are trapped to EL3.

The reset value is unknown.

[5:0] -

Reserved, res0.


To access the MDCR_EL3:

	
MRS <Xt>, MDCR_EL3 ; Read EL3 Monitor Debug Configuration Register
MSR MDCR_EL3, <Xt> ; Write EL3 Monitor Debug Configuration Register
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