The MPIDR_EL1 characteristics are:
Provides an additional core identification mechanism for scheduling purposes in a cluster system.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
The MPIDR_EL1[31:0] is:
Architecturally mapped to the AArch32 MPIDR register. See Multiprocessor Affinity Register.
Mapped to external EDDEVAFF0 register.
MPIDR_EL1[63:32] is mapped to external EDDEVAFF1 register.
MPIDR_EL1 is a 64-bit register.
Figure 4.2 shows the MPIDR_EL1 bit assignments.
Table 4.20 shows the MPIDR_EL1 bit assignments.
Affinity level 3. Highest level affinity field.
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach. This value is:
Affinity level 2. Second highest level affinity field.
Indicates the value read in the CLUSTERIDAFF2 configuration signal.
Affinity level 1. Third highest level affinity field.
Indicates the value read in the CLUSTERIDAFF1 configuration signal.
Affinity level 0. Lowest level affinity field.
Indicates the core number in the Cortex-A53 processor. The possible values are:
To access the MPIDR_EL1:
MRS <Xt>, MPIDR_EL1 ; Read MPIDR_EL1 into Xt
Register access is encoded as follows:
The EDDEVAFF0 and EDDEVAFF1 can be accessed through the internal
memory-mapped interface and the external debug interface, offsets