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Physical Address Register, EL1

The PAR_EL1 characteristics are:

Purpose

The Physical Address returned from an address translation.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RW RW RW RW RW
Configurations

PAR_EL1 is architecturally mapped to AArch32 register PAR(NS). See Physical Address Register.

Attributes

PAR_EL1 is a 64-bit register.

Figure 4.62 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion completes successfully.

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Table 4.111 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion completes successfully.

Table 4.111.  PAR_EL1 pass bit assignments
Bits Name Function
[63:60] AttrH

Defines Normal or Device memory and outer cacheability. Must be used in conjunction with AttrL. The possible values are:

0b0000

Device memory, see Attr[3:0].

0b0100

Normal memory, Outer Non-cacheable.

0b1000

Normal memory, Outer Write-Through Cacheable.

0b1001

Normal memory, Outer Write-Through Cacheable, Outer Write-Allocate.

0b1010

Normal memory, Outer Write-Through Cacheable, Outer Read-Allocate.

0b1011

Normal memory, Outer Write-Through Cacheable, Outer WriteAllocate, Outer Read-Allocate.

0b1100

Normal memory, Outer Write-Back Cacheable.

0b1101

Normal memory, Outer Write-Back Cacheable, Outer Write-Allocate.

0b1110

Normal memory, Outer Write-Back Cacheable, Outer Read-Allocate.

0b1111

Normal memory, Outer Write-Back Cacheable, Outer Write-Allocate, Outer Read-Allocate.

All other values are reserved.

[59:56] AttrL

Defines Device memory, and Inner cacheability. Must be interpreted in conjunction with AttrH. The possible values are:

0b0000

Device (nGnRnE) memory if AttrH is 0b0000. Otherwise this value is reserved.

0b0100

Device (not nGnRnE) memory if AttrH is 0b0000. Otherwise, Normal memory, Inner Non-cacheable.

0b1000

Reserved if AttrH is 0b0000. Otherwise, Normal memory, Inner Write-Through Cacheable.

0b1001

Reserved if AttrH is 0b0000. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Write-Allocate.

0b1010

Reserved if AttrH is 0b0000. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Read-Allocate.

0b1011

Reserved if AttrH is 0b0000. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Write-Allocate, Inner Read-Allocate.

0b1100

Reserved if AttrH is 0b0000. Otherwise, Normal memory, Inner Write-Back Cacheable.

0b1101

Reserved if AttrH is 0b0000. Otherwise, Normal memory, Inner Write-Back Cacheable, Inner Write-Allocate.

0b1110

Reserved if AttrH is 0b0000. Otherwise, Normal memory, Inner Write-Back Cacheable, Inner Read-Allocate.

0b1111

Reserved if AttrH is 0b0000. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Write-Allocate, Inner Read-Allocate.

All other values are reserved.

[55:48] - Reserved, res0.
[47:12] PA Physical address. The Physical Address corresponding to the supplied Virtual Address. Returns address bits[47:12].
[11] - Reserved, res1.
[10] - Reserved, res0.
[9] NS

Non-secure. The NS attribute for a translation table entry read from Secure state.

This bit is unknown for a translation table entry from Non-secure state.

[8:7] SHA

Shareability attribute for the Physical Address returned from a translation table entry. The possible values are:

0b00

Non-shareable.

0b01

Reserved.

0b10

Outer Shareable

0b11

Inner Shareable.

Note

Takes the value of 0b10 for:

  • Any type of device memory.

  • Normal memory with both Inner Non-cacheable and Outer-cacheable attributes.

[6:1] - Reserved, res0.
[0] F

Pass/Fail bit. Indicates whether the conversion completed successfully. This value is:

0

Virtual Address to Physical Address conversion completed successfully.


Figure 4.63 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion is aborted.

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Table 4.112 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion is aborted.

Table 4.112.  PAR_EL1 fail bit assignments
Bits Name Function
[63:12] -

Reserved, res0.

[11] - Reserved, res1.
[10] - Reserved, res0.
[9] S

Stage of fault. Indicates the state where the translation aborted. The possible values are:

0

Translation aborted because of a fault in stage 1 translation.

1

Translation aborted because of a fault in stage 2 translation.

[8] PTW

Indicates a stage 2 fault during a stage 1 table walk. The possible values are:

0

No stage 2 fault during a stage 1 table walk.

1

Translation aborted because of a stage 2 fault during a stage 1 table walk.

[7] - Reserved, res0.
[6:1] FST

Fault status code, as shown in the Data Abort ESR encoding. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

[0] F

Pass/Fail bit. Indicates whether the conversion completed successfully. This value is:

1

Virtual Address to Physical Address conversion aborted.


To access the PAR_EL1:

	
MRS <Xt>, PAR_EL1 ; Read EL1 Physical Address Register
MSR PAR_EL1, <Xt> ; Write EL1 Physical Address Register
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