You copied the Doc URL to your clipboard.

Revision ID Register

The REVIDR_EL1 characteristics are:

Purpose

Provides implementation-specific minor revision information that can be interpreted only in conjunction with the Main ID Register.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RO RO RO RO RO
Configurations

REVIDR_EL1 is architecturally mapped to AArch32 register REVIDR. See Revision ID Register.

Attributes

REVIDR_EL1 is a 32-bit register.

Figure 4.3 shows the REVIDR_EL1 bit assignments.

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.22 shows the REVIDR_EL1 bit assignments.

Table 4.22. REVIDR_EL1 bit assignments
Bits Name Function
[31:0] ID number

Implementation-specific revision information. The reset value is determined by the specific Cortex-A53 MPCore implementation.

0x00000000

Revision code is zero.


To access the REVIDR_EL1:

	
MRS <Xt>, REVIDR_EL1 ; Read REVIDR_EL1 into Xt

Register access is encoded as follows:

Table 4.23. REVIDR_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0000 110

Was this page helpful? Yes No