The REVIDR_EL1 characteristics are:
Provides implementation-specific minor revision information that can be interpreted only in conjunction with the Main ID Register.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
REVIDR_EL1 is architecturally mapped to AArch32 register REVIDR. See Revision ID Register.
REVIDR_EL1 is a 32-bit register.
Figure 4.3 shows the REVIDR_EL1 bit assignments.
Table 4.22 shows the REVIDR_EL1 bit assignments.
Implementation-specific revision information. The reset value is determined by the specific Cortex-A53 MPCore implementation.
To access the REVIDR_EL1:
MRS <Xt>, REVIDR_EL1 ; Read REVIDR_EL1 into Xt
Register access is encoded as follows: