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Secure Configuration Register

The SCR_EL3 characteristics are:

Purpose

Defines the configuration of the security state. SCR_EL3 specifies:

  • Security state of EL0 and EL1, either Secure or Non-secure.

  • Register width at lower exception levels.

  • The exception level that the processor takes exceptions at, if an IRQ, FIQ, or external abort occurs.

SCR_EL3 is part of the Security registers functional group.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW
Configurations

SCR_EL3 is mapped to AArch32 register SCR. See Secure Configuration Register.

Attributes

SCR_EL3 is a 32-bit register.

Figure 4.38 shows the SCR_EL3 bit assignments.

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Table 4.82 shows the SCR_EL3 bit assignments.

Table 4.82. SCR_EL3 bit assignments
Bits Name Function
[31:14] -

Reserved, res0.

[13] TWE

Traps WFE instructions. The possible values are:

0

WFE instructions are not trapped. This is the reset value.

1

WFE instructions executed in AArch32 or AArch64 from EL2, EL1 or EL0 are trapped to EL3 if the instruction would otherwise cause suspension of execution, that is if:

  • The event register is not set.

  • There is not a pending WFE wakeup event.

  • The instruction is not trapped at EL2 or EL1.

See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

[12] TWI

Traps WFI instructions. The possible values are:

0

WFI instructions are not trapped. This is the reset value.

1

WFI instructions executed in AArch32 or AArch64 from EL2, EL1 or EL0 are trapped to EL3 if the instruction would otherwise cause suspension of execution, that is if there is not a pending WFI wakeup event and the instruction is not trapped at EL2 or EL1.

See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

[11] ST

Enable Secure EL1 access to CNTPS_TVAL_EL1, CNTS_CTL_EL1, and CNTPS_CVAL_EL1 registers. The possible values are:

0

Registers accessible only in EL3. This is the reset value.

1

Registers accessible in EL3 and EL1 when SCR_EL3.NS is 0.

[10] RW

Register width control for lower exception levels. The possible values are:

0

Lower levels are all AArch32. This is the reset value.

1

The next lower level is AArch64.

[9] SIF

Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction fetches from Non-secure memory. The possible values are:

0

Secure state instruction fetches from Non-secure memory are permitted. This is the reset value.

1

Secure state instruction fetches from Non-secure memory are not permitted.

[8] HCE

Hyp Call enable. This bit enables the use of HVC instructions. The possible values are:

0

The HVC instruction is undefined at all exception levels. This is the reset value.

1

The HVC instruction is enabled at EL1, EL2 or EL3.

[7] SMD

SMC instruction disable. The possible values are:

0

The SMC instruction is enabled at EL1, EL2, and EL3. This is the reset value.

1

The SMC instruction is undefined at all exception levels. At EL1, in the Non-secure state, the HCR_EL2.TSC bit has priority over this control.

[6] -

Reserved, res0.

[5:4] - Reserved, res1.
[3] EA

External Abort and SError interrupt Routing. This bit controls which mode takes external aborts. The possible values are:

0

External Aborts and SError Interrupts while executing at exception levels other than EL3 are not taken in EL3. This is the reset value.

1

External Aborts and SError Interrupts while executing at all exception levels are taken in EL3.

[2] FIQ

Physical FIQ Routing. The possible values ares:

0

Physical FIQ while executing at exception levels other than EL3 are not taken in EL3. This is the reset value.

1

Physical FIQ while executing at all exception levels are taken in EL3.

[1] IRQ

Physical IRQ Routing. The possible values are:

0

Physical IRQ while executing at exception levels other than EL3 are not taken in EL3.

1

Physical IRQ while executing at all exception levels are taken in EL3.

[0] NS

Non-secure bit. The possible values are. The possible values are:

0

EL0 and EL1 are in Secure state, memory accesses from those exception levels can access Secure memory. This is the reset value.

1

EL0 and EL1 are in Non-secure state, memory accesses from those exception levels cannot access Secure memory.


To access the SCR_EL3:

	
MRS <Xt>, SCR_EL3 ; Read SCR_EL3 into Xt
MSR SCR_EL3, <Xt> ; Write Xt to SCR_EL3
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