You copied the Doc URL to your clipboard.

Secure Debug Enable Register

The SDER32_EL3 characteristics are:

Purpose

Allows access to the AArch32 register SDER only from AArch64 state. Its value has no effect on execution in AArch64 state.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW
Configurations

SDER32_EL3 is architecturally mapped to AArch32 register SDER. See Secure Debug Enable Register.

Attributes

SDER32_EL3 is a 32-bit register.

Figure 4.39 shows the SDER32_EL3 bit assignments.

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.83 shows the SDER32_EL3 bit assignments.

Table 4.83. SDER32_EL3 bit assignments
Bits Name Function
[31:2] - Reserved, res0.
[1] SUNIDEN

Secure User Non-invasive Debug Enable The possible values are:

0

Non-invasive debug not permitted in Secure EL0 mode. This is the Warm reset value.

1

Non-invasive debug permitted in Secure EL0 mode.

[0] SUIDEN

Secure User Invasive Debug Enable. The possible values are:

0

Invasive debug not permitted in Secure EL0 mode. This is the Warm reset value.

1

Invasive debug permitted in Secure EL0 mode.


To access the SDER32_EL3:

	
MRS <Xt>, SDER32_EL3 ; Read SDER32_EL3 into Xt
MSR SDER32_EL3, <Xt> ; Write Xt to SDER32_EL3
Was this page helpful? Yes No