You copied the Doc URL to your clipboard.

System Control Register, EL1

The SCTLR_EL1 characteristics are:

Purpose

Provides top level control of the system, including its memory system at EL1.

SCTLR_EL1 is part of the Virtual memory control registers functional group.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RW RW RW RW RW
Configurations

SCTLR_EL1 is architecturally mapped to AArch32 register SCTLR(NS) See System Control Register.

Attributes

SCTLR_EL1 is a 32-bit register.

Figure 4.28 shows the SCTLR_EL1 bit assignments.

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.72 shows the SCTLR_EL1 bit assignments.

Table 4.72. SCTLR_EL1 bit assignments
Bits Name Function
[31:30] -

Reserved, res0.

[29:28] -

Reserved, res1.

[27] -

Reserved, res0.

[26] UCI

Enables EL0 access to the DC CVAU, DC CIVAC, DC CVAC and IC IVAU instructions in the AArch64 Execution state. The possible values are:

0

EL0 access disabled. This is the reset value.

1

EL0 access enabled.

[25] EE

Exception endianness. The value of this bit controls the endianness for explicit data accesses at EL1. This value also indicates the endianness of the translation table data for translation table lookups. The possible values of this bit are:

0

Little-endian.

1

Big-endian.

The reset value of this bit is determined by the CFGEND configuration pin.

[24] E0E

Endianness of explicit data access at EL0. The possible values are:

0

Explicit data accesses at EL0 are little-endian. This is reset value.

1

Explicit data accesses at EL0 are big-endian.

[23:22] -

Reserved, res1.

[21] -

Reserved, res0.

[20] -

Reserved, res1.

[19] WXN

Write permission implies Execute Never (XN). This bit can be used to require all memory regions with write permissions to be treated as XN. The possible values are:

0

Regions with write permission are not forced XN. This is the reset value.

1

Regions with write permissions are forced XN.

[18] nTWE

WFE non-trapping. The possible values are:

0

A WFE instruction executed at EL0, that, if this bit was set to 1, would permit entry to a low-power state, is trapped to EL1.

1

WFE instructions executed as normal. This is the reset value.

[17] -

Reserved, res0.

[16] nTWI

WFI non-trapping. The possible values are:

0

A WFI instruction executed at EL0, that, if this bit was set to 1, would permit entry to a low-power state, is trapped to EL1.

1

WFI instructions executed as normal. This is the reset value.

[15] UCT

Enables EL0 access to the CTR_EL0 register in AArch64 Execution state. The possible values are:

0

Disables EL0 access to the CTR_EL0 register. This is the reset value.

1

Enables EL0 access to the CTR_EL0 register.

[14] DZE

Enables access to the DC ZVA instruction at EL0. The possible values are:

0

Disables execution access to the DC ZVA instruction at EL0. The instruction is trapped to EL1. This is the reset value.

1

Enables execution access to the DC ZVA instruction at EL0.

[13] -

Reserved, res0.

[12] I

Instruction cache enable. The possible values are:

0

Instruction caches disabled. This is the reset value.

1

Instruction caches enabled.

[11] -

Reserved, res1.

[10] -

Reserved, res0.

[9] UMA

User Mask Access. Controls access to interrupt masks from EL0, when EL0 is using AArch64. The possible values of this bit are:

0

Disable access to the interrupt masks from EL0.

1

Enable access to the interrupt masks from EL0.

[8] SED

SETEND instruction disable. The possible values are:

0

The SETEND instruction is enabled. This is the reset value.

1

The SETEND instruction is undefined.

[7] ITD

IT instruction disable. The possible values are:

0

The IT instruction functionality is enabled. This is the reset value.

1

All encodings of the IT instruction with hw1[3:0]!=1000 are undefined and treated as unallocated.All encodings of the subsequent instruction with the following values for hw1 are undefined (and treated as unallocated):

11xxxxxxxxxxxxxx

All 32-bit instructions, B(2), B(1), Undefined, SVC, Load/Store multiple

1x11xxxxxxxxxxxx

Miscellaneous 16-bit instructions

1x100xxxxxxxxxxx

ADD Rd, PC, #imm

01001xxxxxxxxxxx

LDR Rd, [PC, #imm]

0100x1xxx1111xxx

ADD(4),CMP(3), MOV, BX pc, BLX pc

010001xx1xxxx111

ADD(4),CMP(3), MOV

Contrary to the standard treatment of conditional undefined instructions in the ARM architecture, in this case these instructions are always treated as undefined, regardless of whether the instruction would pass or fail its condition codes as a result of being in an IT block.

[6] THEE
res0

T32EE is not implemented.

[5] CP15BEN

CP15 barrier enable. The possible values are:

0

CP15 barrier operations disabled. Their encodings are undefined.

1

CP15 barrier operations enabled. This is the reset value.

[4] SA0

Enable EL0 stack alignment check. The possible values are:

0

Disable EL0 stack alignment check.

1

Enable EL0 stack alignment check. This is the reset value.

[3] SA

Enable SP alignment check. The possible values are:

0

Disable SP alignment check.

1

Enable SP alignment check. This is the reset value.

[2] C

Cache enable. The possible values are:

0

Data and unified caches disabled. This is the reset value.

1

Data and unified caches enabled.

[1] A

Alignment check enable. The possible values are:

0

Alignment fault checking disabled. This is the reset value.

1

Alignment fault checking enabled.

[0] M

MMU enable. The possible values are:

0

EL1 and EL0 stage 1 MMU disabled. This is the reset value.

1

EL1 and EL0 stage 1 MMU enabled.


To access the SCTLR_EL1:

	
MRS <Xt>, SCTLR_EL1 ; Read SCTLR_EL1 into Xt
MSR SCTLR_EL1, <Xt> ; Write Xt to SCTLR_EL1
Was this page helpful? Yes No