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System Control Register, EL3

The SCTLR_EL3 characteristics are:

Purpose

Provides top level control of the system, including its memory system at EL3.

SCTLR_EL3 is part of the Virtual memory control registers functional group.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW
Configurations

SCTLR_EL3 is mapped to AArch32 register SCTLR(S). See System Control Register.

Attributes

SCTLR_EL3 is a 32-bit register.

Figure 4.37 shows the SCTLR_EL3 bit assignments.

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Table 4.81 shows the SCTRLR_EL3 bit assignments.

Table 4.81.  SCTLR_EL3 bit assignments
Bits Name Function
[31:30] -

Reserved, res0.

[29:28] - Reserved, res1.
[27:26] - Reserved, res0.
[25] EE

Exception endianness. This bit controls the endianness for:

  • Explicit data accesses at EL3.

  • Stage 1 translation table walks at EL3.

The possible values are:

0

Little endian. This is the reset value.

1

Big endian.

[24] - Reserved, res0.
[23:22] - Reserved, res1.
[21:20] - Reserved, res0.
[19] WXN

Force treatment of all memory regions with write permissions as XN. The possible values are:

0

Regions with write permissions are not forced XN. This is the reset value.

1

Regions with write permissions are forced XN.

[18] - Reserved, res1.
[17] -

Reserved, res0.

[16] - Reserved, res1.
[15:13] -

Reserved, res0.

[12] I

Global instruction cache enable. The possible values are:

0

Instruction caches disabled. This is the reset value.

1

Instruction caches enabled.

[11] - Reserved, res1.
[10:6] - Reserved, res0.
[5:4] - Reserved, res1.
[3] SA

Enables stack alignment check. The possible values are:

0

Disables stack alignment check.

1

Enables stack alignment check. This is the reset value.

[2] C

Global enable for data and unifies caches. The possible values are:

0

Disables data and unified caches. This is the reset value.

1

Enables data and unified caches.

[1] A

Enable alignment fault check The possible values are:

0

Disables alignment fault checking. This is the reset value.

1

Enables alignment fault checking.

[0] M

Global enable for the EL3 MMU. The possible values are:

0

Disables EL3 MMU. This is the reset value.

1

Enables EL3 MMU.


To access the SCTLR_EL3:

	
MRS <Xt>, SCTLR_EL3 ; Read SCTLR_EL3 into Xt
MSR SCTLR_EL3, <Xt> ; Write Xt to SCTLR_EL3
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