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Translation Control Register, EL1

The TCR_EL1 characteristics are:

Purpose

Determines which Translation Base Registers defines the base address register for a translation table walk required for stage 1 translation of a memory access from EL0 or EL1 and holds cacheability and shareability information.

TCR_EL1 is part of the Virtual memory control registers functional group.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RW RW RW RW RW
Configurations

TCR_EL1 is architecturally mapped to AArch32 register TTBCR(NS). See Translation Table Base Control Register.

Attributes

TCR_EL1 is a 64-bit register.

Figure 4.44 shows the TCR_EL1 bit assignments.

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Table 4.88 shows the TCR_EL1 bit assignments.

Table 4.88.  TCR_EL1 bit assignments
Bits Name Function
[63:39] -

Reserved, res0.

[38] TBI1

Top Byte Ignored. Indicates whether the top byte of the input address is used for address match for the TTBR1_EL1 region. The possible values are:

0

Top byte used in the address calculation.

1

Top byte ignored in the address calculation.

[37] TBI0

Top Byte Ignored. Indicates whether the top byte of the input address is used for address match for the TTBR0_EL1 region. The possible values are:

0

Top byte used in the address calculation.

1

Top byte ignored in the address calculation.

[36] AS

ASID size. The possible values are:

0

8-bit.

1

16-bit.

[35] -

Reserved, res0.

[34:32] IPS

Intermediate Physical Address Size. The possible values are:

0b000

32 bits, 4GB.

0b001

36 bits, 64GB.

0b010

40 bits, 1TB.

All other values are reserved.

[31:30] TG1

TTBR1_EL1 granule size. The possible values are:

0b00

Reserved.

0b10

4KB.

0b11

64KB.

All other values are not supported.

[29:28] SH1

Shareability attribute for memory associated with translation table walks using TTBR1_EL1. The possible values are:

0b00

Non-shareable.

0b01

Reserved.

0b10

Outer shareable.

0b11

Inner shareable.

[27:26] ORGN1

Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. The possible values are:

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

[25:24] IRGN1

Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. The possible values are:

0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Inner Write-Through Cacheable.

0b11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

[23] EPD1

Translation table walk disable for translations using TTBR1_EL1. Controls whether a translation table walk is performed on a TLB miss for an address that is translated using TTBR1_EL1. The possible values are:

0

Perform translation table walk using TTBR1_EL1.

1

A TLB miss on an address translated from TTBR1_EL1 generates a Translation fault. No translation table walk is performed.

[22] A1

Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The possible values are:

0

TTBR0_EL1.ASID defines the ASID.

1

TTBR1_EL1.ASID defines the ASID.

[21:16] T1SZ

Size offset of the memory region addressed by TTBR1_EL1. The region size is 2(64-T1SZ) bytes.

[15:14] TG0

TTBR0_EL1 granule size. The possible values are:

0b00

4KB.

0b01

64KB.

0b11

Reserved.

All other values are not supported.

[13:12] SH0

Shareability attribute for memory associated with translation table walks using TTBR0_EL1. The possible values are:

0b00

Non-shareable.

0b01

Reserved.

0b10

Outer shareable.

0b11

Inner shareable.

[11:10] ORGN0

Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. The possible values are:

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

[9:8] IRGN0

Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. The possible values are:

0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Inner Write-Through Cacheable.

0b11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

[7] EPD0

Translation table walk disable for translations using TTBR0_EL1. Controls whether a translation table walk is performed on a TLB miss for an address that is translated using TTBR0_EL1. The possible values are:

0

Perform translation table walk using TTBR0_EL1.

1

A TLB miss on an address translated from TTBR0_EL1 generates a Translation fault. No translation table walk is performed.

[6] -

Reserved, res0.

[5:0] T0SZ

Size offset of the memory region addressed by TTBR0_EL1. The region size is 2(64-T0SZ) bytes.


To access the TCR_EL1:

	
MRS <Xt>, TCR_EL1 ; Read TCR_EL1 into Xt
MSR TCR_EL1, <Xt> ; Write Xt to TCR_EL1
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