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Translation Control Register, EL2

The TCR_EL2 characteristics are:

Purpose

Controls translation table walks required for stage 1 translation of a memory access from EL2 and holds cacheability and shareability information.

TCR_EL2 is part of:

  • The Virtual memory control registers functional group.

  • The Hypervisor and virtualization registers functional group.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW RW RW
Configurations

TCR_EL2 is architecturally mapped to AArch32 register HCTR. See Hyp Translation Control Register.

Attributes

TCR_EL2 is a 32-bit register.

Figure 4.45 shows the TCR_EL2 bit assignments.

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Table 4.89 shows the TCR_EL2 bit assignments.

Table 4.89.  TCR_EL2 bit assignments
Bits Name Function
[31] -

Reserved, res1.

[30:24] - Reserved, res0.
[23] -

Reserved, res1.

[22:21] - Reserved, res0.
[20] TBI

Top Byte Ignored. Indicates whether the top byte of the input address is used for address match. The possible values are:

0

Top byte used in the address calculation.

1

Top byte ignored in the address calculation.

[19] - Reserved, res0.
[18:16] PS

Physical address size. The possible values are:

0b000

32 bits, 4 GB.

0b001

36 bits, 64 GB.

0b010

40 bits, 1 TB.

Other values are reserved.

[15:14] TG0

TTBR0_EL2 granule size. The possible values are:

0b00

4 KB.

0b01

64 KB.

0b11

Reserved.

All other values are not supported.

[13:12] SH0

Shareability attribute for memory associated with translation table walks using TTBR0_EL2.

The possible values are:

0b00

Non-shareable.

0b01

Reserved.

0b10

Outer shareable.

0b11

Inner shareable.

[11:10] ORGN0

Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2. The possible values are:

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

[9:8] IRGN0

Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2. The possible values are:

0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Inner Write-Through Cacheable.

0b11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

[7:6] -

Reserved, res0.

[5:0] T0SZ

Size offset of the memory region addressed by TTBR0_EL2. The region size is 2(64-T0SZ) bytes.


To access the TCR_EL2:

	
MRS <Xt>, TCR_EL2 ; Read EL2 Translation Control Register
MSR TCR_EL2, <Xt> ; Write EL2 Translation Control Register
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