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Translation Table Base Register 0, EL3

The TTBR0_EL3 characteristics are:

Purpose

Holds the base address of the translation table for the stage 1 translation of memory accesses from EL3.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW
Configurations

TTBR0_EL3 is mapped to AArch32 register TTBR0 (S). See Translation Table Base Register 0.

Attributes

TTBR0_EL3 is a 64-bit register.

Figure 4.48 shows the TTBR0_EL3 bit assignments.

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Table 4.92 shows the TTBR0_EL3 bit assignments.

Table 4.92. TTBR0_EL3 bit assignments
Bits Name Function
[63:48] -

Reserved, res0.

[47:0] BADDR[47:x]

Translation table base address, bits[47:x]. Bits [x-1:0] are res0.

x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation granule size.

For instructions on how to calculate it, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

The value of x determines the required alignment of the translation table, that must be aligned to 2x bytes.

If bits [x-1:0] are not all zero, this is a misaligned Translation Table Base Address. Its effects are constrained unpredictable, where bits [x-1:0] are treated as if all the bits are zero. The value read back from those bits is the value written.


To access the TTBR0_EL3:

	
MRS <Xt>, TTBR0_EL3 ; Read TTBR0_EL3 into Xt
MSR TTBR0_EL3, <Xt> ; Write Xt to TTBR0_EL3
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