You copied the Doc URL to your clipboard.

Vector Base Address Register, EL1

The VBAR_EL1 characteristics are:

Purpose

Holds the exception base address for any exception that is taken to EL1.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RW RW RW RW RW
Configurations

The VBAR_EL1[31:0] is architecturally mapped to the Non-secure AArch32 VBAR register. See Vector Base Address Register.

Attributes

VBAR_EL1 is a 64-bit register.

Figure 4.65 shows the VBAR_EL1 bit assignments.

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.116 shows the VBAR_EL1 bit assignments.

Table 4.116.  VBAR_EL1 bit assignments
Bits Name Function
[63:11] Vector base address

Base address of the exception vectors for exceptions taken in this exception level.

[10:0] -

Reserved, res0.


To access the VBAR_EL1:

	
MRS <Xt>, VBAR_EL1 ; Read VBAR_EL1 into Xt
MSR VBAR_EL1, <Xt> ; Write Xt to VBAR_EL1
Was this page helpful? Yes No