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Virtualization Translation Control Register, EL2

The VTCR_EL2 characteristics are:

Purpose

Controls the translation table walks required for the stage 2 translation of memory accesses from Non-secure EL0 and EL1, and holds cacheability and shareability information for the accesses.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW RW RW

Any of the bits in VTCR_EL2 are permitted to be cached in a TLB.

Configurations

VTCR_EL2 is architecturally mapped to AArch32 register VTCR. See Virtualization Translation Control Register.

Attributes

VTCR_EL2 is a 32-bit register.

Figure 4.46 shows the VTCR_EL2 bit assignments.

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Table 4.90 shows the VTCR_EL2 bit assignments.

Table 4.90. VTCR_EL2 bit assignments
Bits Name Function
[31] -

Reserved, res1.

[30:19] -

Reserved, res0.

[18:16] PS

Physical Address Size. The possible values are:

0b000

32 bits, 4 GB.

0b001

36 bits, 64 GB.

0b010

40 bits, 1 TB.

All other values are reserved.

[15:14] TG0

Granule size for the corresponding VTTBR_EL2.

0b00

4 KB.

0b01

64 KB.

0b11

Reserved.

All other values are not supported.

[13:12] SH0

Shareability attribute for memory associated with translation table walks using VTTBR_EL2.

0b00

Non-shareable.

0b01

Reserved.

0b10

Outer Shareable.

0b11

Inner Shareable.

[11:10] ORGN0

Outer cacheability attribute for memory associated with translation table walks using VTTBR_EL2.

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

[9:8] IRGN0

Inner cacheability attribute for memory associated with translation table walks using VTTBR_EL2.

0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Inner Write-Through Cacheable.

0b11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

[7:6] SL0 Starting level of the VTCR_EL2 addressed region.
[5:0] T0SZ

The size offset of the memory region addressed by VTTBR_EL2. The region size is 2(64-T0SZ) bytes.


To access the VTCR_EL2:

	
MRS <Xt>, VTCR_EL2 ; Read VTCR_EL2 into Xt
MSR VTCR_EL2, <Xt> ; Write Xt to VTCR_EL2
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