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AArch64 performance monitor registers

Table 4.10 shows the performance monitor registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in Table 4.10.

Table 4.10. AArch64 performance monitor registers
Name Type Reset Width Description
PMCR_EL0 RW 0x41033000 32

Performance Monitors Control Register

PMCNTENSET_EL0 RW UNK 32 Performance Monitors Count Enable Set Register [a]
PMCNTENCLR_EL0 RW UNK 32 Performance Monitors Count Enable Clear Register [a]
PMOVSCLR_EL0 RW UNK 32

Performance Monitors Overflow Flag Status Clear Register [a]

PMSWINC_EL0 WO - 32

Performance Monitors Software Increment Register [a]

PMSELR_EL0 RW UNK 32

Performance Monitors Event Counter Selection Register [a]

PMCEID0_EL0 RO 0x67FFBFFF[b] 32

Performance Monitors Common Event Identification Register 0

PMCEID1_EL0 RO 0x00000000 32 Performance Monitors Common Event Identification Register 1[a]
PMCCNTR_EL0 RW UNK 64

Performance Monitors Cycle Counter[a]

PMXEVTYPER_EL0 RW UNK 32

Performance Monitors Selected Event Type and Filter Register [a]

PMXEVCNTR_EL0 RW UNK 32

Performance Monitors Selected Event Counter Register [a]

PMUSERENR_EL0 RW 0x00000000 32

Performance Monitors User Enable Register [a]

PMINTENSET_EL1 RW UNK 32 Performance Monitors Interrupt Enable Set Register [a]
PMINTENCLR_EL1 RW UNK 32 Performance Monitors Interrupt Enable Clear Register [a]
PMOVSSET_EL0 RW UNK 32

Performance Monitors Overflow Flag Status Set Register [a]

PMEVCNTR0_EL0 RW UNK 32 Performance Monitor Event Count Registers
PMEVCNTR1_EL0 RW UNK 32
PMEVCNTR2_EL0 RW UNK 32
PMEVCNTR3_EL0 RW UNK 32
PMEVCNTR4_EL0 RW UNK 32
PMEVCNTR5_EL0 RW UNK 32
PMEVTYPER0_EL0 RW UNK 32

Performance Monitor Event Type Registers

PMEVTYPER1_EL0 RW UNK 32
PMEVTYPER2_EL0 RW UNK 32
PMEVTYPER3_EL0 RW UNK 32
PMEVTYPER4_EL0 RW UNK 32
PMEVTYPER5_EL0 RW UNK 32
PMCCFILTR_EL0 RW 0x00000000 32 Performance Monitors Cycle Count Filter Register [a]

[a] See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

[b] The reset value is 0x663FBFFF if the Cortex-A53 processor has not been configured with an L2 cache.


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