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AArch64 secure registers

Table 4.12 shows the secure registers in AArch64 state.

Table 4.12. AArch64 security registers
Name Type Reset Width Description
SCR_EL3 RW 0x00000000 32

Secure Configuration Register

SDER32_EL3 RW 0x00000000 32

Secure Debug Enable Register

CPTR_EL3 RW 0x00000000[a] 32 Architectural Feature Trap Register, EL3
MDCR_EL3 RW 0x00000000 32

Monitor Debug Configuration Register, EL3

AFSR0_EL3 RW 0x00000000 32 Auxiliary Fault Status Register 0, EL1, EL2 and EL3
AFSR1_EL3 RW 0x00000000 32 Auxiliary Fault Status Register 1, EL1, EL2 and EL3
VBAR_EL3 RW 0x0000000000000000 64 Vector Base Address Register, EL3

[a] Reset value is 0x00000000 if Advanced SIMD and Floating point are implemented, 0x00000400 otherwise.

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