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AArch64 thread registers

Table 4.16 shows the thread registers in AArch64 state. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information about these operations.

Table 4.16. AArch64 miscellaneous system control operations
Name Type Reset Width Description
TPIDR_EL0 RW UNK 64

Thread Pointer/ID Register, EL0

TPIDR_EL1 RW UNK 64

Thread Pointer/ID Register, EL1

TPIDRRO_EL0 RW UNK 64

Thread Pointer/ID Register, Read-Only, EL0

TPIDR_EL2 RW UNK 64

Thread Pointer/ID Register, EL2

TPIDR_EL3 RW UNK 64

Thread Pointer/ID Register, EL3


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