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AArch64 virtual memory control registers

Table 4.3 shows the virtual memory control registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in Table 4.3.

Table 4.3. AArch64 virtual memory control registers
Name Type Reset Width Description
SCTLR_EL1 RW 0x00C50838[a] 32

System Control Register, EL1

SCTLR_EL2 RW 0x30C50838[b] 32 System Control Register, EL2
SCTLR_EL3 RW 0x00C50838 [a] 32 System Control Register, EL3
TTBR0_EL1 RW UNK 64

Translation Table Base Register 0, EL1

TTBR1_EL1 RW UNK 64 Translation Table Base Register 1
TCR_EL1 RW UNK 64 Translation Control Register, EL1
TTBR0_EL2 RW UNK 64 Translation Table Base Address Register 0, EL2[c]
TCR_EL2 RW UNK 32 Translation Control Register, EL2
VTTBR_EL2 RW UNK 64

Virtualization Translation Table Base Address Register, EL2[c]

VTCR_EL2 RW UNK 32 Virtualization Translation Control Register, EL2
TTBR0_EL3 RW UNK 64 Translation Table Base Register 0, EL3
TCR_EL3 RW UNK 32 Translation Control Register, EL3
MAIR_EL1 RW UNK 64

Memory Attribute Indirection Register, EL1

AMAIR_EL1 RW 0x00000000 64 Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
MAIR_EL2 RW UNK 64

Memory Attribute Indirection Register, EL2

AMAIR_EL2 RW 0x00000000 64 Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
MAIR_EL3 RW UNK 64

Memory Attribute Indirection Register, EL3

AMAIR_EL3 RW 0x00000000 64 Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
CONTEXTIDR_EL1 RW UNK 32

Context ID Register, EL1[c]

[a] The reset value depends on primary inputs CFGTE and CFGEND. Table 4.3 assumes these signals are LOW.

[b] The reset value depends on primary inputs CFGTE, CFGEND and VINITHI. Table 4.3 assumes these signals are LOW.

[c] See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.


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