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11.10. External debug interface

The system can access memory-mapped debug registers through the APB interface. The APB interface is compliant with the AMBA 4 APB interface.

Figure 11.21 shows the debug interface implemented in the Cortex-A53 processor. For more information on these signals, see the ARM® CoreSight™ Architecture Specification.

Figure 11.21. External debug interface, including APBv3 slave port

Figure 11.21. External debug interface, including
APBv3 slave port

This section describes external debug interface in:

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