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11.10.1. Debug memory map

The basic memory map supports up to four cores in the cluster. Table 11.27 shows the address mapping for the Cortex-A53 processor debug APB components when configured for v8 Debug memory map.

Each component in the table requires 4KB, and uses the bottom 4KB of each 64KB region. The remaining 60KB of each region is reserved.

Table 11.27. Address mapping for APB components
Address offset [21:0]Component[a]
0x000000 - 0x000FFFCortex-A53 APB ROM table
0x010000 - 0x010FFFCPU 0 Debug
0x020000 - 0x020FFFCPU 0 CTI
0x030000 - 0x030FFFCPU 0 PMU
0x040000 - 0x040FFFCPU 0 Trace
0x041000 - 0x10FFFFReserved
0x110000 - 0x110FFFCPU 1 Debug
0x120000 - 0x120FFFCPU 1 CTI
0x130000 - 0x130FFFCPU 1 PMU
0x140000 - 0x140FFFCPU 1 Trace
0x141000 - 0x20FFFFReserved
0x210000 - 0x210FFFCPU 2 Debug
0x220000 - 0x220FFFCPU 2 CTI
0x230000 - 0x230FFFCPU 2 PMU
0x240000 - 0x240FFFCPU 2 Trace
0x241000 - 0x30FFFFReserved
0x310000 - 0x310FFFCPU 3 Debug
0x320000 - 0x320FFFCPU 3 CTI
0x330000 - 0x330FFFCPU 3 PMU
0x340000 - 0x340FFFCPU 3 Trace
0x341000 - 0x3FFFFFReserved

[a] Indicates the mapped component if present, otherwise reserved.


Table 11.28 shows the address mapping for the Cortex-A53 processor debug APB components when configured for v7 Debug memory map.

Table 11.28. Address mapping for APB components
Address offset [21:0]Component[a]
0x00000 - 0x00FFFCortex-A53 APB ROM table
0x01000 - 0x07FFFReserved for other debug components
0x08000 - 0x0FFFFReserved for future expansion
0x10000 - 0x10FFFCPU 0 Debug
0x11000 - 0x11FFFCPU 0 PMU
0x12000 - 0x12FFFCPU 1 Debug
0x13000 - 0x13FFFCPU 1 PMU
0x14000 - 0x14FFFCPU 2 Debug
0x15000 - 0x15FFFCPU 2 PMU
0x16000 - 0x16FFFCPU 3 Debug
0x17000 - 0x17FFFCPU 3 PMU
0x18000 - 0x18FFFCPU 0 CTI
0x19000 - 0x19FFFCPU 1 CTI
0x1A000 - 0x1AFFFCPU 2 CTI
0x1B000 - 0x1BFFFCPU 3 CTI
0x1C000 - 0x1CFFFCPU 0 Trace
0x1D000 - 0x1DFFFCPU 1 Trace
0x1E000 - 0x1EFFFCPU 2 Trace
0x1F000 - 0x1FFFFCPU 3 Trace

[a] Indicates the mapped component if present, otherwise reserved.


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