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13.8.43. Power Down Status Register

The TRCPDSR characteristics are:


Indicates the power down status of the ETM trace unit.

Usage constraints

There are no usage constraints.


Available in all configurations.


See the register summary in Table 13.3.

Figure 13.45 shows the TRCPDSR bit assignments.

Figure 13.45. TRCPDSR bit assignments

Figure 13.45. TRCPDSR bit assignments

Table 13.46 shows the TRCPDSR bit assignments.

Table 13.46. TRCPDSR bit assignments
[31:6]-Reserved, res0.

OS lock status.


The OS Lock is unlocked.


The OS Lock is locked.

[4:2]-Reserved, res0.

Sticky power down state.


Trace register power has not been removed since the TRCPDSR was last read.


Trace register power has been removed since the TRCPDSR was last read.

This bit is set to 1 when power to the ETM trace unit registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR.


Indicates the ETM trace unit is powered:


ETM trace unit is not powered. The trace registers are not accessible and they all return an error response.


ETM trace unit is powered. All registers are accessible.

If a system implementation allows the ETM trace unit to be powered off independently of the debug power domain, the system must handle accesses to the ETM trace unit appropriately.

The TRCPDSR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x314.

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