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2.1.6. Data side memory system

This section describes the following:

Data Cache Unit

The Data Cache Unit (DCU) consists of the following sub-blocks:

  • The Level 1 (L1) data cache controller, that generates the control signals for the associated embedded tag, data, and dirty RAMs, and arbitrates between the different sources requesting access to the memory resources. The data cache is 4-way set associative and uses a Physically Indexed, Physically Tagged (PIPT) scheme for lookup that enables unambiguous address management in the system.

  • The load/store pipeline that interfaces with the DPU and main TLB.

  • The system controller that performs cache and TLB maintenance operations directly on the data cache and on the instruction cache through an interface with the IFU.

  • An interface to receive coherency requests from the Snoop Control Unit (SCU).

The data cache has the following features:

  • Pseudo-random cache replacement policy.

  • Streaming of sequential data because of multiple word load instructions, for example LDM, LDRD, LDP and VLDM.

  • Critical word first linefill on a cache miss.

See Chapter 6 Level 1 Memory System for more information.

If the CPU cache protection configuration is implemented, the L1 Data cache tag RAMs and dirty RAMs are protected by parity bits. The L1 Data cache data RAMs are protected using Error Correction Codes (ECC). The ECC scheme is Single Error Correct Double Error Detect (SECDED).

The DCU includes a combined local and global exclusive monitor, which is used by the Load-Exclusive/ Store-Exclusive instructions. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for information about these instructions.

Store Buffer

The Store Buffer (STB) holds store operations when they have left the load/store pipeline and have been committed by the DPU. The STB can request access to the cache RAMs in the DCU, request the BIU to initiate linefills, or request the BIU to write out the data on the external write channel. External data writes are through the SCU.

The STB can merge:

  • Several store transactions into a single transaction if they are to the same 128-bit aligned address.

  • Multiple writes into an AXI or CHI write burst.

The STB is also used to queue maintenance operations before they are broadcast to other cores in the cluster.

See Chapter 6 Level 1 Memory System for more information.

Bus Interface Unit and SCU interface

The Bus Interface Unit (BIU) contains the SCU interface and buffers to decouple the interface from the cache and STB. The BIU interface and the SCU always operate at the processor frequency.

See Chapter 6 Level 1 Memory System for more information.

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