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2.1.7. L2 memory system

The Cortex-A53 L2 memory system contains the L2 cache pipeline and all logic required to maintain memory coherence between the cores of the cluster. It has the following features:

  • An SCU that connects the cores to the external memory system through the master memory interface. The SCU maintains data cache coherency between the cores and arbitrates L2 requests from the cores.

    When the Cortex-A53 processor is implemented with a single core, it still includes the Snoop Control Unit (SCU). See Implementation options for more information.


    The SCU does not support hardware management of coherency of the instruction caches. Instruction cache linefills perform coherent reads, however, there is no coherency management of data held in the instruction cache.

  • An optional L2 cache that:

    • Has a cache RAM size of 128KB, 256KB, 512KB, 1MB, or 2MB.

    • Is 16-way set associative.

    • Supports 64 byte cache lines.

  • A 512-bit wide fetch path from the L2 cache.

  • A single 128-bit wide master interface to external memory that:

    • Can be implemented using the AMBA 4 ACE or AMBA 5 CHI architectures.

    • Supports integer ratios of the processor clock period up to and including 1:1.

    • Supports a 40-bit physical address range.

  • An optional 128-bit wide I/O coherent ACP interface that can allocate to the L2 cache.

See Chapter 7 Level 2 Memory System for more information.

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