The PMCEID0 characteristics are:
- Purpose
Defines which common architectural and common microarchitectural feature events are implemented.
- Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2 EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
Config Config RO RO RO RO RO This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.
- Configurations
The PMCEID0 is architecturally mapped to:
The AArch64 register PMCEID0_EL0. See Performance Monitors Common Event Identification Register 0.
The external register PMCEID0_EL0.
There is one copy of this register that is used in both Secure and Non-secure states.
- Attributes
PMCEID0 is a 32-bit register.
Figure 12.6 shows the PMCEID0 bit assignments.
Table 12.11 shows the PMCEID0 bit assignments with event implemented or not implemented when the associated bit is set to 1 or 0. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information about these events.
| Bits | Name | Function |
|---|---|---|
| [31:0] | CE[31:0] | Common architectural and microarchitectural feature events that can be counted by the PMU event counters. For each bit described in Table 12.12, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0. |
| Bit | Event number | Event mnemonic | Description |
|---|---|---|---|
| [31] | 0x1F | L1D_CACHE_ALLOCATE | L1 Data cache allocate:
|
| [30] | 0x1E | CHAIN | Chain. For odd-numbered counters, counts once for each overflow of the preceding even-numbered counter. For even-numbered counters, does not count:
|
| [29] | 0x1D | BUS_CYCLES | Bus cycle:
|
| [28] | 0x1C | TTBR_WRITE_RETIRED | TTBR write, architecturally executed, condition check pass - write to translation table base:
|
| [27] | 0x1B | INST_SPEC | Instruction speculatively executed:
|
| [26] | 0x1A | MEMORY_ERROR | Local memory error:
|
| [25] | 0x19 | BUS_ACCESS | Bus access:
|
| [24] | 0x18 | L2D_CACHE_WB | L2 Data cache Write-Back:
|
| [23] | 0x17 | L2D_CACHE_REFILL | L2 Data cache refill:
|
| [22] | 0x16 | L2D_CACHE | L2 Data cache access:
|
| [21] | 0x15 | L1D_CACHE_WB | L1 Data cache Write-Back:
|
| [20] | 0x14 | L1I_CACHE | L1 Instruction cache access:
|
| [19] | 0x13 | MEM_ACCESS | Data memory access:
|
| [18] | 0x12 | BR_PRED | Predictable branch speculatively executed:
|
| [17] | 0x11 | CPU_CYCLES | Cycle:
|
| [16] | 0x10 | BR_MIS_PRED | Mispredicted or not predicted branch speculatively executed:
|
| [15] | 0x0F | UNALIGNED_LDST_RETIRED | Instruction architecturally executed, condition check pass - unaligned load or store:
|
| [14] | 0x0E | BR_RETURN_RETIRED | Instruction architecturally executed, condition check pass - procedure return:
|
| [13] | 0x0D | BR_IMMED_RETIRED | Instruction architecturally executed - immediate branch:
|
| [12] | 0x0C | PC_WRITE_RETIRED | Instruction architecturally executed, condition check pass - software change of the PC:
|
| [11] | 0x0B | CID_WRITE_RETIRED | Instruction architecturally executed, condition check pass - write to CONTEXTIDR:
|
| [10] | 0x0A | EXC_RETURN | Instruction architecturally executed, condition check pass - exception return:
|
| [9] | 0x09 | EXC_TAKEN | Exception taken:
|
| [8] | 0x08 | INST_RETIRED | Instruction architecturally executed:
|
| [7] | 0x07 | ST_RETIRED | Instruction architecturally executed, condition check pass - store:
|
| [6] | 0x06 | LD_RETIRED | Instruction architecturally executed, condition check pass - load:
|
| [5] | 0x05 | L1D_TLB_REFILL | L1 Data TLB refill:
|
| [4] | 0x04 | L1D_CACHE | L1 Data cache access:
|
| [3] | 0x03 | L1D_CACHE_REFILL | L1 Data cache refill:
|
| [2] | 0x02 | L1I_TLB_REFILL | L1 Instruction TLB refill:
|
| [1] | 0x01 | L1I_CACHE_REFILL | L1 Instruction cache refill:
|
| [0] | 0x00 | SW_INCR | Instruction architecturally executed, condition check pass - software increment:
|
To access the PMCEID0:
MRC p15,0,<Rt>,c9,c12,6 ; Read PMCEID0 into Rt
The PMCEID0 can be accessed through the internal memory-mapped
interface and the external debug interface, offset 0xE20.