The PMCEID1 characteristics are:
Defines which common architectural and common microarchitectural feature events are implemented.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
Config Config RO RO RO RO RO
This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1
The PMCEID1 is architecturally mapped to:
The AArch32 register PMCEID1_EL0. See Performance Monitors Common Event Identification Register 1.
The external register PMCEID1_EL0.
There is one copy of this register that is used in both Secure and Non-secure states.
PMCEID1 is a 32-bit register.
Figure 12.7 shows the PMCEID1 bit assignments
Table 12.13 shows the PMCEID1 bit assignments.
Common architectural and microarchitectural feature events that can be counted by the PMU event counters.
For each bit described in Table 12.14, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.
|Bit||Event number||Event mnemonic||Description|
To access the PMCEID1:
MRC p15,0,<Rt>,c9,c12,7 ; Read PMCEID1 into Rt
The PMCEID1 can be accessed through the internal memory-mapped
interface and the external debug interface, offset