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12.7. Memory-mapped register summary

Table 12.15 shows the PMU registers that are accessible through the internal memory-mapped interface and the external debug interface. For those registers not described in this chapter, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.

Table 12.15. Memory-mapped PMU register summary
OffsetNameTypeDescription
0x000PMEVCNTR0_EL0RW

Performance Monitor Event Count Register 0

0x004--Reserved
0x008PMEVCNTR1_EL0RW

Performance Monitor Event Count Register 1

0x00C--Reserved
0x010PMEVCNTR2_EL0RW

Performance Monitor Event Count Register 2

0x014--Reserved
0x018PMEVCNTR3_EL0RW

Performance Monitor Event Count Register 3

0x01C--Reserved
0x020PMEVCNTR4_EL0RW

Performance Monitor Event Count Register 4

0x024--Reserved
0x028PMEVCNTR5_EL0RW

Performance Monitor Event Count Register 5

0x02C-0xF4--Reserved
0x0F8PMCCNTR_EL0[31:0]RW

Performance Monitor Cycle Count Register

0x0FCPMCCNTR_EL0[63:32]RW
0x100-0x3FC--Reserved
0x400PMEVTYPER0_EL0RWPerformance Monitor Event Type Register
0x404PMEVTYPER1_EL0RW
0x408PMEVTYPER2_EL0RW
0x40CPMEVTYPER3_EL0RW
0x410PMEVTYPER4_EL0RW
0x414PMEVTYPER5_EL0RW
0x418-0x478--Reserved
0x47CPMCCFILTR_EL0RW

Performance Monitor Cycle Count Filter Register

0x480-0xBFC--Reserved
0xC00PMCNTENSET_EL0RW

Performance Monitor Count Enable Set Register

0xC04-0xC1C--Reserved
0xC20PMCNTENCLR_EL0RW

Performance Monitor Count Enable Clear Register

0xC24-0xC3C--Reserved
0xC40PMINTENSET_EL1RW

Performance Monitor Interrupt Enable Set Register

0xC44-0xC5C--Reserved
0xC60PMINTENCLR_EL1RW

Performance Monitor Interrupt Enable Clear Register

0xC64-0xC7C--Reserved
0xC80PMOVSCLR_EL0RW

Performance Monitor Overflow Flag Status Register

0xC84-0xC9C--Reserved
0xCA0PMSWINC_EL0WO

Performance Monitor Software Increment Register

0xCA4-0xCBC--Reserved
0xCC0PMOVSSET_EL0RWPerformance Monitor Overflow Flag Status Set Register
0xCC4-0xDFC--Reserved
0xE00PMCFGRROPerformance Monitor Configuration Register
0xE04PMCR_EL0[a]RW

Performance Monitors Control Register

0xE08-0xE1C--Reserved
0xE20PMCEID0_EL0ROPerformance Monitors Common Event Identification Register 0
0xE24PMCEID1_EL0ROPerformance Monitor Common Event Identification Register 1
0xE28-0xFA4--Reserved
0xFA8PMDEVAFF0ROPerformance Monitors Device Affinity Register 0, see Multiprocessor Affinity Register
0xFACPMDEVAFF1ROPerformance Monitors Device Affinity Register 1, res0
0xFB0PMLARWO

Performance Monitor Lock Access Register

0xFB4PMLSRROPerformance Monitor Lock Status Register
0xFB8PMAUTHSTATUSRO

Performance Monitor Authentication Status Register

0xFBCPMDEVARCH Performance Monitor Device Architecture Register
0xFC0-0xFC8--Reserved
0xFCCPMDEVTYPERO

Performance Monitor Device Type Register

0xFD0PMPIDR4ROPeripheral Identification Register 4
0xFD4PMPIDR5ROPeripheral Identification Register 5-7
0xFD8PMPIDR6RO
0xFDCPMPIDR7RO
0xFE0PMPIDR0ROPeripheral Identification Register 0
0xFE4PMPIDR1ROPeripheral Identification Register 1
0xFE8PMPIDR2ROPeripheral Identification Register 2
0xFECPMPIDR3ROPeripheral Identification Register 3
0xFF0PMCIDR0ROComponent Identification Register 0
0xFF4PMCIDR1ROComponent Identification Register 1
0xFF8PMCIDR2ROComponent Identification Register 2
0xFFCPMCIDR3ROComponent Identification Register 3

[a] This register is distinct from the PMCR_EL0 system register. It does not have the same value.


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