The CCSIDR characteristics are:
Provides information about the architecture of the caches.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
If CSSELR indicates a cache that is not implemented, then on a read of the CCSIDR the behavior is constrained unpredictable, and can be one of the following:
The CCSIDR read is treated as
The CCSIDR read is undefined.
The CCSIDR read returns an unknown value (preferred).
CCSIDR is architecturally mapped to AArch64 register CCSIDR_EL1. See Cache Size ID Register.
There is one copy of this register that is used in both Secure and Non-secure states.
The implementation includes one CCSIDR for each cache that it can access. CSSELR selects which Cache Size ID Register is accessible.
CCSIDR is a 32-bit register.
Figure 4.92 shows the CCSIDR bit assignments.
Table 4.190 shows the CCSIDR bit assignments.
Indicates support for Write-Through:
Indicates support for Write-Back:
Indicates support for Read-Allocation:
Indicates support for Write-Allocation:
Indicates the number of sets in cache - 1. Therefore, a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2.
Indicates the associativity of cache - 1. Therefore, a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2.
Indicates the (log2 (number of words in cache line)) - 2:
Table 4.191 shows the individual bit field and complete register encodings for the CCSIDR. The CSSELR determines which CCSIDR to select.
|CSSELR||Cache||Size||Complete register encoding||Register bit field encoding|
|L1 Data cache||8KB||0||1||1||1|
|L1 Instruction cache||8KB||0||0||1||0|
To access the CCSIDR:
MRC p15, 1, <Rt>, c0, c0, 0 ; Read CCSIDR into Rt
Register access is encoded as follows: