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4.5.20. Cache Size ID Register

The CCSIDR characteristics are:

Purpose

Provides information about the architecture of the caches.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RORORORORO

If CSSELR indicates a cache that is not implemented, then on a read of the CCSIDR the behavior is constrained unpredictable, and can be one of the following:

  • The CCSIDR read is treated as NOP.

  • The CCSIDR read is undefined.

  • The CCSIDR read returns an unknown value (preferred).

Configurations

CCSIDR is architecturally mapped to AArch64 register CCSIDR_EL1. See Cache Size ID Register.

There is one copy of this register that is used in both Secure and Non-secure states.

The implementation includes one CCSIDR for each cache that it can access. CSSELR selects which Cache Size ID Register is accessible.

Attributes

CCSIDR is a 32-bit register.

Figure 4.92 shows the CCSIDR bit assignments.

Figure 4.92. CCSIDR bit assignments

Figure 4.92. CCSIDR bit assignments

Table 4.190 shows the CCSIDR bit assignments.

Table 4.190. CCSIDR bit assignments
BitsNameFunction
[31]WT

Indicates support for Write-Through:

0

Cache level does not support Write-Through.

[30]WB

Indicates support for Write-Back:

0

Cache level does not support Write-Back.

1

Cache level supports Write-Back.

[29]RA

Indicates support for Read-Allocation:

0

Cache level does not support Read-Allocation.

1

Cache level supports Read-Allocation.

[28]WA

Indicates support for Write-Allocation:

0

Cache level does not support Write-Allocation.

1

Cache level supports Write-Allocation.

[27:13]NumSets[a]

Indicates the number of sets in cache - 1. Therefore, a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2.

[12:3]Associativity[a]

Indicates the associativity of cache - 1. Therefore, a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2.

[2:0]LineSize[a]

Indicates the (log2 (number of words in cache line)) - 2:

0b010

16 words per line.

[a] For more information about encoding, see Table 4.191.


Table 4.191 shows the individual bit field and complete register encodings for the CCSIDR. The CSSELR determines which CCSIDR to select.

Table 4.191. CCSIDR encodings
CSSELRCache SizeComplete register encodingRegister bit field encoding
WTWBRAWANumSetsAssociativityLineSize
0x0L1 Data cache8KB0x7003E01A01110x001F0x0030x2
16KB0x7007E01A0x003F0x0030x2
32KB0x700FE01A0x007F0x0030x2
64KB0x701FE01A0x00FF0x0030x2
0x1L1 Instruction cache 8KB0x2007E00A00100x003F0x0010x2
16KB0x200FE00A0x007F0x0010x2
32KB0x201FE00A0x00FF0x0010x2
64KB0x203FE00A0x001F0x0010x2
0x2L2 cache128KB0x700FE07A01110x007F0x00F0x2
256KB0x701FE07A0x00FF0x00F0x2
512KB0x703FE07A0x01FF0x00F0x2
1024KB0x707FE07A0x03FF0x00F0x2
2048KB0x70FFE07A0x07FF0x00F0x2
0x3-0xFReserved---------

To access the CCSIDR:

MRC p15, 1, <Rt>, c0, c0, 0 ; Read CCSIDR into Rt

Register access is encoded as follows:

Table 4.192. CCSIDR access encoding
coprocopc1CRnCRmopc2
111100100000000000