The HPFAR characteristics are:
Holds the faulting IPA for some aborts on a stage 2 translation taken to Hyp mode.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - - RW RW -
Execution in any Non-secure mode other than Hyp mode makes HPFAR unknown.
HPFAR is architecturally mapped to AArch64 register HPFAR_EL2[31:0]. See Hypervisor IPA Fault Address Register, EL2.
HPFAR is a 32-bit register.
Figure 4.130 shows the HPFAR bit assignments.
Table 4.238 shows the HPFAR bit assignments.
Bits [39:12] of the faulting intermediate physical address
To access the HPFAR:
MRC p15, 4, <Rt>, c6, c0, 4 ; Read HPFAR into Rt MCR p15, 4, <Rt>, c6, c0, 4 ; Write Rt to HPFAR