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4.4.21. AArch32 Fault handling registers

Table 4.149 shows the Fault handling registers in the AArch32 Execution state.

Table 4.149. Fault handling registers
NameCRnOp1CRmOp2ResetDescription
DFSRc50c00UNK

Data Fault Status Register

IFSR   1UNK

Instruction Fault Status Register

ADFSR  c100x00000000

Auxiliary Data Fault Status Register

AIFSR   10x00000000

Auxiliary Instruction Fault Status Register

DFARc60c00UNK

Data Fault Address Register, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile

IFAR   2UNK

Instruction Fault Address Register, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile


The Virtualization registers include additional fault handling registers. For more information see AArch32 Virtualization registers.

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