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4.4.19. AArch32 Identification registers

Table 4.147 shows the identification registers.

Table 4.147. Identification registers
NameCRnOp1CRmOp2ResetDescription
MIDRc00c000x410FD034

Main ID Register

CTR   10x84448004

Cache Type Register

TCMTR   20x00000000

TCM Type Register

TLBTR   30x00000000

TLB Type Register

MPIDR   5-[a]

Multiprocessor Affinity Register

REVIDR   60x00000000Revision ID Register
ID_PFR0  c100x00000131

Processor Feature Register 0

ID_PFR1   10x10011011[b]

Processor Feature Register 0

ID_DFR0   20x03010066

Debug Feature Register 0

ID_AFR0   30x00000000Auxiliary Feature Register 0
ID_MMFR0   40x10201105

Memory Model Feature Register 0

ID_MMFR1   50x40000000

Memory Model Feature Register 1

ID_MMFR2   60x01260000

Memory Model Feature Register 2

ID_MMFR3   70x02102211

Memory Model Feature Register 3

ID_ISAR0  c200x02101110

Instruction Set Attribute Register 0

ID_ISAR1   10x13112111

Instruction Set Attribute Register 1

ID_ISAR2   20x21232042

Instruction Set Attribute Register 2

ID_ISAR3   30x01112131

Instruction Set Attribute Register 3

ID_ISAR4   40x00011142

Instruction Set Attribute Register 4

ID_ISAR5c00c250x00011121[c]

Instruction Set Attribute Register 5

CCSIDR 1c00-

Cache Size ID Register

CLIDR   10x0A200023[d]

Cache Level ID Register

AIDR   70x00000000

Auxiliary ID Register

CSSELR 2c000x00000000Cache Size Selection Register

[a] The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of cores that the device implements.

[b] Bits [31:28] are 0x1 if the GIC CPU interface is enabled, and 0x0 otherwise.

[c] ID_ISAR5 has the value 0x00010001 if the Cryptography Extension is not implemented and enabled.

[d] The value is 0x09200003 if the L2 cache is not implemented.


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