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4.4.30. AArch32 Implementation defined registers

Table 4.157 shows the 32-bit wide implementation defined registers. These registers provide test features and any required configuration options specific to the Cortex-A53 processor.

Table 4.157. Memory access registers
NameCRnOp1CRmOp2ResetDescription
L2CTLRc91c02-[a]

L2 Control Register

L2ECTLR30x00000000L2 Extended Control Register
L2ACTLRc151c000x80000000[b]L2 Auxiliary Control Register
CBARc30-[a]Configuration Base Address Register
CDBGDR03[c]c00UNKData Register 0, see Direct access to internal memory
CDBGDR1  1UNKData Register 1, see Direct access to internal memory
CDBGDR2  2UNKData Register 2, see Direct access to internal memory
CDBGDCT c20UNKData Cache Tag Read Operation Register, see Direct access to internal memory
CDBGICT   1UNKInstruction Cache Tag Read Operation Register, see Direct access to internal memory
CDBGDCD   c40UNKData Cache Data Read Operation Register, see Direct access to internal memory
CDBGICD c41UNKInstruction Cache Data Read Operation Register, see Direct access to internal memory
CDBGTD  2UNKTLB Data Read Operation Register, see Direct access to internal memory
CPUACTLR-0c15-0x00000000090CA000CPU Auxiliary Control Register
CPUECTLR-1c15-0x0000 0000 0000 0000CPU Extended Control Register
CPUMERRSR-2c15--CPU Memory Error Syndrome Register
L2MERRSR-3c15--L2 Memory Error Syndrome Register

[a] The reset value depends on the processor configuration.

[b] This is the reset value for an ACE interface. For a CHI interface the reset value is 0x 80004008.

[c] See Direct access to internal memory for information on how these registers are used.


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