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4.4.25. AArch32 Performance monitor registers

Table 4.153 shows the performance monitor registers. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table 4.153. Performance monitor registers
NameCRnOp1CRmOp2ResetDescription
PMCRc90c1200x41033000

Performance Monitors Control Register

PMCNTENSET   1UNK

Performance Monitors Count Enable Set Register

PMCNTENCLR   2UNK

Performance Monitors Count Enable Clear Register

PMOVSR   3UNK

Performance Monitors Overflow Flag Status Register

PMSWINC   4UNK

Performance Monitors Software Increment Register

PMSELR   5UNK

Performance Monitors Event Counter Selection Register

PMCEID0   60x67FFBFFF[a]Performance Monitors Common Event Identification Register 0
PMCEID1   70x00000000Performance Monitors Common Event Identification Register 1
PMCCNTR  c130UNK

Performance Monitors Cycle Count Register

PMXEVTYPER   1UNKPerformance Monitors Selected Event Type Register
PMXEVCNTR   2UNK

Performance Monitors Event Count Registers

PMUSERENR  c1400x00000000

Performance Monitors User Enable Register

PMINTENSET1UNK

Performance Monitors Interrupt Enable Set Register

PMINTENCLR2UNKPerformance Monitors Interrupt Enable Clear Register
PMOVSSET3UNK

Performance Monitor Overflow Flag Status Set Register

PMEVCNTR0c140c80UNK

Performance Monitors Event Count Register 0

PMEVCNTR11UNK 
PMEVCNTR22UNK 
PMEVCNTR33UNK 
PMEVCNTR44UNK 
PMEVCNTR55UNK 
PMEVTYPER0c120UNKPerformance Monitors Selected Event Type Register 0
PMEVTYPER11UNK 
PMEVTYPER22UNK 
PMEVTYPER33UNK 
PMEVTYPER44UNK 
PMEVTYPER55UNK 
PMCCFILTRc1570x00000000Performance Monitors Cycle Count Filter Register

[a] The reset value is 0x663FBFFF if L2 cache is not implemented.


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