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4.4.26. AArch32 Secure registers

Table 4.154 shows the Secure registers. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table 4.154. Security registers
NameCRnOp1CRmOp2ResetDescription
SCRc10c100x00000000

Secure Configuration Register

SDER   1UNKSecure Debug Enable Register
NSACR   2

0x00000000[a]

Non-Secure Access Control Register

VBARc120c000x00000000

Vector Base Address Register

MVBAR   1UNK

Monitor Vector Base Address Register

ISR  c10UNK

Interrupt Status Register

[a] If EL3 is AArch64 then the NSACR reads as 0x00000C00.


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